Unverified Commit 589ed631 authored by Schuyler Eldridge's avatar Schuyler Eldridge Committed by GitHub
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Simplify assertKnownWidth to Verilog test (#3078)



Change the assertKnownWidth and assertInferredWidth test utility methods
to check Verilog directly as opposed to doing a full Verilator
compilation.  This dramatically improves the speed of these tests and
should help triage failures if there are problems.

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@sifive.com>
parent 6dc091b9
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