Commit d9415785 authored by Schuyler Eldridge's avatar Schuyler Eldridge Committed by Jack Koenig
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Fix EulerTour for circuits with one module (#736)



A circuit with a single module would fail to properly compute BV RMQs due
to a divide by zero bug.

This changes the computation of the number of blocks an Euler Tour is
broken up into to be, at minimum, one.

This also changes one of the test cases ("wire with source and sink in the
same module") to exercise this.

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
parent ec00c4b9
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