Unverified Commit c6740926 authored by mergify[bot]'s avatar mergify[bot] Committed by GitHub
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Don't invalidate ExtModule ports in an explicitInvalidate = true context (backport #2795) (#2798)

* Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)

* Don't invalidate ExtModule ports in an explicitInvalidate = true context

ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`.

(cherry picked from commit 8e24a281

)

# Conflicts:
#	core/src/main/scala/chisel3/BlackBox.scala
#	src/test/scala/chiselTests/ExtModule.scala
#	src/test/scala/chiselTests/aop/InjectionSpec.scala

* Resolve backport conflicts

Co-authored-by: default avatarJared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
parent b961900d
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