This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.

Defaulting to 0 prevents Linux from booting

There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.

Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.

Various priv-1.10 changes

https://github.com/riscv/riscv-isa-manual/commit/a2a3346e7345619efe3b5e8620d4a87c72d21ad0

This reverts commit 0538dc77.

This reverts commit fb6498f2.

Bump the year for the SiFive license

* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.

This way a program started by the debugger still has the DTB handy.

This allows more flexibility e.g. considering the ROM as part of other
devices.

* jtag: Add ucb-art/chisel-jtag to junctions.

* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch

* jtag: move to a top-level package

Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.

This allows it to be optimized like an adder, improving QoR when it
is on the critical path.