- Jul 18, 2017
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Colin Schmidt authored
also update list of files expected to be seen in generated-src
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Howard Mao authored
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- Jul 15, 2017
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Wesley W. Terpstra authored
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- Jul 14, 2017
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Richard Xia authored
PLIC: Add maxPri as well as ndev in DTS
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Richard Xia authored
Rename offchip-interrupts to external-interrupts.
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Megan Wachs authored
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Richard Xia authored
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Shreesha Srinath authored
BootROM parameters currently control the boot rom address, size, and the hang which essentially sets the reset vector. This commit allows specifying different parameter values as required.
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Megan Wachs authored
I used the singular because there is really only one max priority
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Megan Wachs authored
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- Jul 13, 2017
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Wesley W. Terpstra authored
In particular, it is ok if no slaves actually need FIFO fixing. It is also ok if none of those fixed are FIFO.
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Wesley W. Terpstra authored
Fifo fixer configable
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- Jul 11, 2017
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Wesley W. Terpstra authored
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Megan Wachs authored
regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was (#855)
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- Jul 10, 2017
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Jim Lawson authored
Use chisel3 Clock() method.
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- Jul 08, 2017
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Wesley W. Terpstra authored
SRAM errors
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Jim Lawson authored
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Henry Cook authored
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
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- Jul 07, 2017
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Megan Wachs authored
PLIC: (undefZero=true) Don't allow addresses to alias
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Megan Wachs authored
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
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Andrew Waterman authored
L1 memory system improvements
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Andrew Waterman authored
This makes single-step exceptions higher-priority than debug interrupts.
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Andrew Waterman authored
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- Jul 06, 2017
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
Cache the error bit in the tag array; report precisely on access.
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