Use modified Chisel to require invalidation in compatibility code but
only on IOs

Fix ITIM deallocation during I$ refill causing data corruption

Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.

The workaround described in commit 3db06630
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.

This subsumes commit 3db06630.

This reverts commit 3db06630.

Verify blocker width

tile: bus blocker needs to know width

debug: bump riscv-tools/riscv-tests/debug for Priv test fixes

...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.

* debug: Update macros from spec

* debug: some corrections in the auto-generated files

* debug: update renamed fields

* Debug: implement the implicit ebreak option for small program buffers

* debug: clean up some unused code and add more require() explanations

* debug: make implicit ebreak false

* debug: Add the havereset/haveresetack functionality

* debug: program buffer can still be 16 even if there is an implicit ebreak

Bumped riscv-tools/riscv-isa-sim

axi4: add an Xbar

This is a follow-up to PR #1108.

Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.

* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard

If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.

needs to use RocketTileParams.hartid instead of zipWithIndex

bump tools for .align 2 fix in riscv-tests

Provide option to support AMOs only on I/O, not DTIM/D$

Frontend improvements

More ITIM error-handling improvements