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+ DontCare s1_dout as its Mux is not fully connected;
+ + also remove "init = " (with param name) as new chisel-plugin in 3.6 won't compile;

feat: convert groundtest to chisel3
wrap io declaration and use explicit import

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

+ also remove "init = " and "next = " (with param name) as new chisel-plugin in 3.6 won't compile.
+ DontCare the IO as there are some unconnected IOs in some occasions.

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* refactor IBuf to chisel3.

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

convert prci directory to use chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* feat: convert unittest to chisel3

Convert unittest subdir to use chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

- Converts the regmapper directory to chisel3
- fix import style and add IO wrapper
- Add IO wrapper for declaration, and use explicit import
- remove whitespaces and brackets

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Bump the formal subdirectory to chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Add TLResourceRemover

* RegionReplicator: only check prefix when relevant

* Support incoherent access to AXI4 extmem through sbus

RoccBlackBox fixes for: 1) incorrect signal assigned to rocc_resp_bits_rd; 2) incorrect behavior in synthesis result (tested on FPGA) (#3035)

Removed TraceGen in HeterogeneousTileExampleConfig

Convert toaxe.py to Python3

Co-authored-by: Jiuyang liu <liujiuyang1994@gmail.com>