Add a bug to make sure tests are functional

Crossing: deprecate instead of delete the heavily used IntSyncCrossingSink API for asynchronous interrupt crossings

Synchronizers: update interrupt crossings to deal with the requirement that async crossings are truly async and marked with SynchronizerPrimitiveShiftReg

Rocket Core DCache TileLink: require FIFO to allVolatile regions

GroundTestTileParams Some(ICacheParams)

Rocket Core DCache TileLink: dont require Fifo just yet

Fix offsets of DMOuter registers in Object Model.

TLFIFOFixer.Policy requireFifo

The previous Object Model implementation did not account for the relative offset
of the dmOuter register address block. This commit adds some logic to translate
the offsets into absolute addresses.

Like 37a3161b,
this is also just for post-silicon debug purposes.  Disabling prefetch
doesn't add much extra PSD benefit beyond disabling speculative refill,
because the latter disables prefetching on speculative accesses already,
leaving only next-line prefetches following non-speculative refills.
But it is worth something.

AXIS fixes

Commit queue

Features
* Reset inference now supports last connect semantics

Fixes
* FirrtlOptions and CircuitOptions no longer serialized to anno JSON file