Remove vsim/emulator flows, add simple make verilog flow (backport #3494)

Remove SCIE interface (backport #3499)

* Remove vsim/emulator flows, add simple make verilog flowx

* Remove unnecessary dependencies from Makefile'

(cherry picked from commit 4a1715eb)

(cherry picked from commit d4775722)

Connect all s1_data fields in SimpleHellaIF (backport #3497)

Fix Makefrag for mill cross-compile (backport #3489)

Make StoreGen support narrow typ field (copy #3479)

Suppress SourceShrinker require if no shrinking is to be done (copy #3485)

(cherry picked from commit 1d69e6db)

(cherry picked from commit ec106af4)

This makes it a bit easier to use the StoreGen circuit. StoreGen shouldn't error if the `typ` argument is narrower than `maxSize` would normally permit.

(cherry picked from commit 9a416a16)

(cherry picked from commit a8663bc0)

Sync master with dev

Fixes for latest chisel

add WithScratchpadsBaseAddress to alter rocket core dtim address

fix PLIC 0-bit connection

add WithNoSimulationTimeout

Support rocket cache rowBits != sbusWidth

remove linting package from RegisteredLibrary

Rocc csr fix

- migrate to mill 0.11
- bump hardfloat and cde submodule
- Cross Compile Chisel 5

remove donttouch

* remove import Chisel from Nodes

* cloneTypeFull in BundleBrdige

* better name for diplomatic node and don't care them by default