Fix RVC/uncacheable instruction memory performance bug

9c1d1269 was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.

Allow TL fuzzing range to be overridden

Pipeline AXI4 MMIO

Reduce pathological RVC stalls

Add PutPartial support to DTIM

I'm going to change the AMOALU API, and so I'm removing dependent dead code.

As with integer ALU, shave off some muxing.

AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.

If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.

Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.

Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant