This should make hierarchical place and route easier.

This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.

TL pipeline MMIO

So don't stall as though there were.

Update monitor spec

Ignore TL-C

We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.

The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.

ahb: rewrote TLToAHB to avoid retracting requests on stall