TLToAXI4: treat DECERR as denied when possible

- In priv-1.11, mstatus.MPP is WARL, not WLRL
- Fix polarity of mcounteren/scounteren
- Misc. improvements unrelated to correctness

SFENCE-with-rs1 still uses the request port because it needs the CAM.

This disentangles it from target-machine stdout.

Previously, setting a counteren bit to 0 would enable the counter
and setting it to 1 would disable it.  This patch fixes the bug.

Remove GetMeMyModule hack in favor of Chisel API

PhysicalFilter: fix re-use of Grant sink IDs

See https://github.com/riscv/riscv-isa-manual/commit/32b74b7a02e492c48a910ba0d20bcc52155b0616

This change specifically prevents writing H (2) to mstatus.MPP for
systems with S-mode.  There is no change for systems without S-mode.

And of course dcsr.PRV should be treated the same way.

AXI4: add an optional non-standard 'corrupt' signal

The latency between the CacheCork Grant and the LLC GrantAck is
typically quite small, as the LLC already has an MSHR waiting.

* util: pad MaskGen when lgSize.width < lg(lgBytes)

works around a deficiency of UIntToOH in chisel3

(pad is broken)

(0 width literal 0 is broken)

Remove sim-only warning in Pow2ClockDivider

Remove outdated comment, now that ClockDivider2 uses a blackbox

* adding elaborated config transform

* moved the LOCAL_EXTERNAL_INTERRUPTS and GLOBAL_EXTERNAL_INTERRUPTS to an interrupt obj. Changed an arg name

riscv-tests: bump for fix in multi-hart test

* PSDTestMode: in Debug Module, bypass dmactive reset during PSDTestMode

Debug: fix polarity of dmactive as reset

* ResetCatchAndSync: alwayas apply DFT bypass to flops inputs

Fixup cases where Acquire.NtoB is incorrectly promoted to Grant.toT

Previously, using the BusBypass, the PhysicalFilter tried to cut all
traffic (including B+C). This was wrong.

Now, we carefully wait until A=>D is idle, then swallow denied traffic.
The injected traffic thus respects order and we swallow any GrantAcks.

This device will soon not be derived from the BusBypass.