tile: boundary buffers ended up in wrong scope

Revamped Register Router

new API target for collapsing IO peripherals into a single trait

Refactor TLBusWrapper and CrossingHelper

Move subsystem.SubsystemClockCrossing => diplomacy.ClockCrossingType
Put abstract CrossingHelper base class in diplomacy
Make concrete AXI4CrossingHelper, TLCrossingHelper, IntCrossingHelper
Replace CrossingWrapper with AXI4CrossingWrapper, TLCrossingWrapper

BundleBridge and CrossingWrapper API cleanups (pt 2)

diplomacy: desugar BundleBridge -- it was too confusing

Sometimes more typing is better.

Clock Crossings: make API more flexible with CrossingHelper

chisel3 changes:
* Direct translation of ChiselIR to FIRRTL
* Driver support for emitting Protobuf
* Better error message for calling return in a when block

firrtl changes:
* Escaped single quotes supported in ExtModule RawParams
* Partial fix to RemoveWires when reg depends on wire
* Parser performance improvements
* Protobuf serialization and deserialization
* Fix annotation renaming for empty aggregates
* Improved code generation for smem wmode and [w]mask ports
* InferWidths performance improvement
* Some user errors no longer reported as "internal errors"
* Add annotation for combinational dependencies between top-level ports
* InstanceGraph is now deterministic

chisel3 changes:
* Direct translation of ChiselIR to FIRRTL
* Driver support for emitting Protobuf
* Better error message for calling return in a when block

firrtl changes:
* Escaped single quotes supported in ExtModule RawParams
* Partial fix to RemoveWires when reg depends on wire
* Parser performance improvements
* Protobuf serialization and deserialization
* Fix annotation renaming for empty aggregates
* Improved code generation for smem wmode and [w]mask ports
* InferWidths performance improvement
* Some user errors no longer reported as "internal errors"
* Add annotation for combinational dependencies between top-level ports
* InstanceGraph is now deterministic