Commits · om-rtlmodule-update · github.com / chipsalliance / rocket-chip

Dec 18, 2018
- adding default None's to the OMRTL schemas · 8e7a7074
  Derek Pappas authored Dec 17, 2018
  
  8e7a7074
Dec 08, 2018
- merge · c954e847
  Derek Pappas authored Dec 07, 2018
  
  c954e847
- Merge pull request #1729 from freechipsproject/dcache-qor · dbfb1636
  Andrew Waterman authored Dec 07, 2018
```
Remove a D$ ECC critical path
```
  dbfb1636
Dec 06, 2018
- Fix URL in README.md in FPGA section. (#1734) · b50561d9
  Michael Maloney authored Dec 05, 2018
  
  b50561d9
- added isa u spec (#1735) · 165a6f48
  Derek Pappas authored Dec 05, 2018
  
  165a6f48
Dec 05, 2018
- Merge pull request #1715 from freechipsproject/debug-hart-arrays · 65328937
  Ernie Edgar authored Dec 04, 2018
```
Added hart array feature
```
  65328937
- Added hart array feature · 02df475a
  Ernie Edgar authored Nov 20, 2018
  
  02df475a
Dec 04, 2018
- refactoring (#1732) · 29286d9d
  Derek Pappas authored Dec 03, 2018
  
  29286d9d
- new om for rams (#1731) · bbbe91c2
  Derek Pappas authored Dec 03, 2018
  
  bbbe91c2
- Merge pull request #1730 from freechipsproject/misc-fixes · 0c2664ce
  Wesley W. Terpstra authored Dec 03, 2018
```
Fix a few issues with multi-chip designs
```
  0c2664ce
Dec 02, 2018
- AddressAdjuster: fix untested and broken code · 6ba11a31
  Wesley W. Terpstra authored Nov 30, 2018
  
  6ba11a31
- Pipeline D$ ECC -> tag-update path · 4e741ebf
  Andrew Waterman authored Dec 01, 2018
```
This actually saves hardware...
```
  4e741ebf
- Inline the D$ arbiters · 6d939b05
  Andrew Waterman authored Dec 01, 2018
```
These are always on the critical path, and inlining them provides
more opportunity to optimize the control paths in some flows.

Note this doesn't do anything useful without invoking the
firrtl InlineInstances transform.
```
  6d939b05
- Remove a D$ ECC critical path introduced in 29954c6f · c00874c3
  Andrew Waterman authored Dec 01, 2018
  
  c00874c3
Dec 01, 2018
- Merge pull request #1728 from freechipsproject/tile-output-interrupts · 7990d8ba
  Henry Cook authored Nov 30, 2018
```
Tile Notification Nodes
```
  7990d8ba
- tlram: fix notify index bit width · c90a809f
  Henry Cook authored Nov 30, 2018
  
  c90a809f
- tilelink: ram can notify of ecc errors · 57255de6
  Henry Cook authored Nov 30, 2018
  
  57255de6
- ecc: add params case class · 714155f2
  Henry Cook authored Nov 30, 2018
  
  714155f2
- Nomi5 (#1726) · 7292969b
  Derek Pappas authored Nov 30, 2018
```
* adding getOMComponents to ports

* fixing formatting

* created a new getOMPortMemoryRegions

* cosmetic
```
  7292969b
Nov 30, 2018
- tile: all tiles have notification nodes · 1ec033af
  Henry Cook authored Nov 29, 2018
  
  1ec033af
- tile: tileControlAddr is now tile param named beuAddr · 1f1b35b2
  Henry Cook authored Nov 29, 2018
  
  1f1b35b2
- tile: trace port exists unconditionally · ef4c42be
  Henry Cook authored Nov 29, 2018
  
  ef4c42be
- subsystem: BankedL2Params.coherenceManager returns Option[IntOutwardNode] · 52bc980e
  Henry Cook authored Nov 29, 2018
  
  52bc980e
- interrupts: add xbar factory · 12f45cb0
  Henry Cook authored Nov 29, 2018
  
  12f45cb0
Nov 29, 2018
- Tiles: place at the top of the chip graph · 2303e93e
  Wesley W. Terpstra authored Nov 28, 2018
  
  2303e93e
- AddressAdjuster: report which slaves have conflicting width · 16a94678
  Wesley W. Terpstra authored Nov 28, 2018
  
  16a94678
- AXI4ToTL: always select the error device with the largest transfer · b50b1959
  Wesley W. Terpstra authored Nov 28, 2018
  
  b50b1959
- Bump firrtl (#1719) · e03605a9
  Jack Koenig authored Nov 28, 2018
```
Major changes:
* Target (Named deprecated)
* RegisteredTransform
* Cats herded in emitted Verilog
* Bug fixes
```
  e03605a9
Nov 28, 2018
- Merge pull request #1723 from freechipsproject/event_covers · ab893da7
  Sandeep Rajendran authored Nov 27, 2018
```
Fix event covers to eliminate dead covers
```
  ab893da7
- Fix event covers to eliminate dead covers · c9c37120
  Sandeep Rajendran authored Nov 27, 2018
  
  c9c37120
- tile: beu addr is rocekt tile param · f026df71
  Henry Cook authored Nov 27, 2018
  
  f026df71
- tile: move BEU from rocket to tile · ed9adcbc
  Henry Cook authored Nov 27, 2018
  
  ed9adcbc
Nov 27, 2018
- Merge pull request #1712 from freechipsproject/priv-stuff · 3915e158
  Andrew Waterman authored Nov 26, 2018
```
Priv arch enhancements
```
  3915e158
- Remove legacy CSR names · c3b2815d
  Andrew Waterman authored Nov 26, 2018
  
  c3b2815d
- Add PAUSE hint · c2559881
  Andrew Waterman authored Nov 26, 2018
  
  c2559881
Nov 26, 2018
- Merge remote-tracking branch 'origin/master' into nomi6 · 739fe046
  Derek Pappas authored Nov 26, 2018
  
  739fe046
Nov 25, 2018
- D$ optimization: don't drain store buffer if merge opportunity pending · 29954c6f
  Andrew Waterman authored Nov 19, 2018
  
  29954c6f
- optionally expose tile-level cease signal · bbde864b
  Andrew Waterman authored Nov 20, 2018
  
  bbde864b
- D$: add some more advisory signals to help pipeline scheduling · 2bfe9582
  Andrew Waterman authored Nov 19, 2018
  
  2bfe9582
Nov 23, 2018
- adding OMRTLModule · b28607f1
  Derek Pappas authored Nov 22, 2018
  
  b28607f1