- Dec 01, 2018
-
-
Derek Pappas authored
-
Derek Pappas authored
* adding getOMComponents to ports * fixing formatting * created a new getOMPortMemoryRegions * cosmetic
-
- Nov 29, 2018
-
-
Jack Koenig authored
Major changes: * Target (Named deprecated) * RegisteredTransform * Cats herded in emitted Verilog * Bug fixes
-
- Nov 28, 2018
-
-
Sandeep Rajendran authored
Fix event covers to eliminate dead covers
-
Sandeep Rajendran authored
-
- Nov 27, 2018
-
-
Andrew Waterman authored
Priv arch enhancements
-
Andrew Waterman authored
-
Andrew Waterman authored
-
- Nov 25, 2018
-
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
-
- Nov 22, 2018
-
-
Wesley W. Terpstra authored
-
Jack Koenig authored
groupBy considered harmful
-
Andrew Waterman authored
This flushes the D$. It is only meant for power-down and it is only supported on systems without S-mode.
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
After retiring this instruction, no further instructions will retire until reset (including debugging).
-
Andrew Waterman authored
We'll leave the old definitions for a short grace period.
-
Andrew Waterman authored
Clock-gate the debug module using the dmactive signal
-
Derek Pappas authored
-
Derek Pappas authored
-
- Nov 21, 2018
-
-
Andrew Waterman authored
-
Wesley W. Terpstra authored
Power queues
-
- Nov 20, 2018
-
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
Necessary when a feed-forward multi-stage pipeline feeds a LPQ.
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-
Wesley W. Terpstra authored
-