- Mar 25, 2020
-
-
Megan Wachs authored
-
- Mar 23, 2020
-
-
Megan Wachs authored
-
Megan Wachs authored
JTAG Debug Transport: asynchronously reset flops that need to work with no clock edges to avoid violating tile link protocol. Also use chiselName to give predictable naming within withClockAndReset blocks
-
- Mar 21, 2020
-
-
Megan Wachs authored
-
Megan Wachs authored
-
- Mar 19, 2020
-
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Megan Wachs authored
TLBusBypass: calculate the min latency as the minimum of both the normal and bypass device, otherwise you can get assertion failures when using the bypass path
-
Megan Wachs authored
-
Ernie Edgar authored
-
Jack Koenig authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Megan Wachs authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Ernie Edgar authored
-
Jack Koenig authored
Adds LazyModule.withClock, LazyModule.withReset, and LazyModule.withClockAndReset to support setting custom clocks and resets for LazyModuleImps
-