I forgot to add the test code to the C emulator that actually makes this work.

We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.

Without this I don't get rebuilds when toching a file in CDE.

This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).

This reverts commit 4dad5b8b.

The commit breaks the build.

This reverts commit 4d0f941d.

The commit breaks the build.

Bump junctions, for a chisel3 fix

Chisel 3 support

Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.

This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.

 * DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable

Support torture regressions

It looks like Chisel fails when I try to run it in parallel.  This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.

Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.

This change allows the other simulation targets (the emulator and the FPGA
simulator) to be run just like the Verilog simulator could be before.

Support make-3.82 and newer

make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests".  This patch changes the hex file
rules to ensure they match between the two versions of make.

I've tried this with both make-3.81 and make-4.1, and they both work for me.

In order to have the buildbot support various types of failures it needs
to run different commands.  Rather than modifying the regression script
to have a bunch of arguments I've just gone and made a makefile for
regressions instead.

This doesn't run torture right now because that's broken, but I'll add
support soon.