Remove deprecated RegisterRouter APIs

Sync master into dev

Fix build.

Fix Chisel deprecated APIs

Update README.md

Fix outdated technical report link.

Update ECC SRAM to improve throughput on full write

Change a_sublane to also check the mask to see if the transaction a partial write. Improves throughput in cases when the full bus is being utilized

fixing tech report broken link

Support Tile Clusters (tree-like hierarchies) 

Remove the unused outer argument in HellaCacheBundle

Support vector-units w/o L1D$ access (copy #3537)

SContext is remaps to HContext when in VSMode

* Fix the mapping when we access scontext or hcontext to ensure we don't switch targets.
* Add comment to indicate why we are mapping the S to VS and VS to S.

Remove Scalar Crypto and BitManip (copy #3532)

(cherry picked from commit 218ae0aa)

(cherry picked from commit 5bef59a8)

# Conflicts:
#	src/main/scala/tile/Core.scala

(cherry picked from commit 74dd9b19)

(cherry picked from commit df66c19e)

Support vector-units w/o L1D$ access

Bump to Chisel 5.1

Support RocketChip build Chisel from source