* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1

BusWrapper API Update

RegFieldDesc: Emit enumerations into JSON if they exist

Fix mapping of acquire/release AMOs to fence operations

Add jtag_vpi.c to sources for vsim

h/t @mwachs5

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Added functional covers

AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO.  These had been swapped.  This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).

Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations.  For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Implement misa.C proposal

This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.

In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after.  Previously, we reported the exception
on the store's PC, but the store occurred anyway.  This probably
hasn't been problematic in practice because most stores are
idempotent.

Support fLen > xLen

This is a holdover from before we had built the functional unit.