https://github.com/riscv/riscv-v-spec/commit/b8cd98bc9467617b6653583116b2dfe9eefb2f51

This describes whether non-memory instructions support nonzero vstart values.

jchang0 3 days ago Member
I don't think this def is useful. What would be useful is the && version (so erase the "any" part of this def and use && instead)

https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5

We must clear the credit flops during reset.

- supported by TileLink
- supported by AXI4
- partially supported by interrupts

Add CreditedIO to support register-register interfacing for AXI4 and TL

RVV 1.0: reorder fields in vtype

https://github.com/riscv/riscv-v-spec/commit/b8cd98bc9467617b6653583116b2dfe9eefb2f51

Add OMVectorExtension.vstartALU field

This describes whether non-memory instructions support nonzero vstart values.

Changed the function called cover to mincover. Tightened the bound for the fragmenter by adding shrinktransfer. Added comment.

Update RVV whole-register load/store opcodes

https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5