* Allows the BTB to exactly match the PC pipeline of the I$.

   * BOOM will now override Rocket's BTB and supply its own BTB predictions.
   * Requires a Parameter in BaseTile.

   * Currently, Rocket's CSR uses retireWidth to set hpm events increment Width.
   * BOOM's configs must then set its desired PerfIncWidth.
   * Addresses rocket-chip/issues/733 (albiet, in a heavy-handed manner).

   - A BOOM core has its own TLB. Which needs a TL2 edge. And a PTW port.
   - Add edge implicit input to Core.
   - Widen CoreIO to accept a ptw_tlb port.
   - Modify RocketCoreParams to handle wider fetchWidths, retireWidths.
   - Hack PTW requestor count to accommodate extra PTW port.
   - Wire up PTW requestor to the core's TLB in the Tile.

becase reqs can be invalidated

It's redundant with the new scheme, so just adds HW for no reason.

We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.

Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (#554)