Implement misa.C proposal

This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.

In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after.  Previously, we reported the exception
on the store's PC, but the store occurred anyway.  This probably
hasn't been problematic in practice because most stores are
idempotent.

Support fLen > xLen

This is a holdover from before we had built the functional unit.

Give Rocket priority over DTIM TL port

The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline.  Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads.  Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.

RegFieldDesc: fix the output produced for undescribed registers

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Reduce Debug Module "flags"

Error: don't be an exception wrt. caching

Probably not a smart thing to build, but not illegal!

If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.

Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.

Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.

more detailed RegField descriptions

TLRegMapper: emit a JSON file describing the register fields