remove depending on explicit SBUS

Use sortedSlaves in some TL helpers

Fix AXI4 Xbar elaboration error due to missing fields

Resolves https://github.com/chipsalliance/rocket-chip/issues/3548.

Modularize PMA-checking functionality

Fence for RoCC on rocc-csr writes

Add hardware debug ROB

Remove deprecated RegisterRouter APIs

Sync master into dev

Co-authored-by: Jerry Zhao <qwertyuiopghb@gmail.com>

Co-authored-by: Jerry Zhao <qwertyuiopghb@gmail.com>

Fix build.

Fix Chisel deprecated APIs

(Only for integer registers)

Update README.md

Fix outdated technical report link.

Update ECC SRAM to improve throughput on full write

Change a_sublane to also check the mask to see if the transaction a partial write. Improves throughput in cases when the full bus is being utilized

fixing tech report broken link

Support Tile Clusters (tree-like hierarchies) 

Remove the unused outer argument in HellaCacheBundle

Support vector-units w/o L1D$ access (copy #3537)

SContext is remaps to HContext when in VSMode