Commits · cfa1d63a2fcc65f3a1fdb03f3478254cd318e60d · github.com / chipsalliance / rocket-chip

Aug 28, 2020
- readme: clarify example config location (#2620) · cfa1d63a
  Henry Cook authored Aug 27, 2020
  
  cfa1d63a
- Merge pull request #2574 from ncppd/configurable-L1-TLB-v1 · c98c330f
  John Ingalls authored Aug 27, 2020
```
L1 TLB: Add support for configurable L1 TLB (sets/ways)
```
  c98c330f
Aug 27, 2020
- L1 TLB: Rename nTLBEntries to nTLBWays · c82518eb
  Nikos Ch. Papadopoulos authored Aug 27, 2020
  
  c82518eb
- L1 TLB: Add support for configurable L1 TLB by the number of sets and ways · 5483823c
  ncppd authored Jul 24, 2020
  
  5483823c
Aug 26, 2020
- Merge pull request #2619 from chipsalliance/ptw_refill_ready · 3176ed81
  John Ingalls authored Aug 25, 2020
```
PTW: wait for L2TLB refill before searching
```
  3176ed81
Aug 25, 2020
- PTW l2_refill block Arb ready · f478998f
  John Ingalls authored Aug 24, 2020
  
  f478998f
- Merge pull request #2610 from chipsalliance/clockdivider-fix · d6a5dc39
  Jiuyang Liu authored Aug 25, 2020
```
bug fix for ClockDivider
```
  d6a5dc39
Aug 23, 2020
- Merge pull request #2604 from chipsalliance/node_doc_sequencer · 6f0cf546
  Jiuyang Liu authored Aug 23, 2020
```
Nodes Documentation (see #2308 #2560)
```
  6f0cf546
- Review details. · 003a42f6
  Jiuyang liu authored Aug 22, 2020
  
  003a42f6
Aug 22, 2020
- update for review. · b6bc1973
  Jiuyang liu authored Aug 22, 2020
  
  b6bc1973
- Improve MixedNode ScalaDoc · ec464538
  Jack Koenig authored Aug 14, 2020
  
  ec464538
- fix for rebase · 17f43654
  Jiuyang liu authored Aug 14, 2020
  
  17f43654
- update for review. · 7fe539a7
  Jiuyang liu authored Aug 14, 2020
  
  7fe539a7
- add some links to MixedNode. · 7a656ed6
  Jiuyang liu authored Jul 27, 2020
  
  7a656ed6
- recall of MixedNode call graph. · 46bf4898
  Jiuyang liu authored Jul 27, 2020
  
  46bf4898
- some tweaks after looking at output · aa08070c
  Megan Wachs authored Jul 16, 2020
  
  aa08070c
- Nodes documentation: Ok with content, working on warnings now · 7349d4f3
  Megan Wachs authored Jul 16, 2020
  
  7349d4f3
- More edits, WIP · 205b81fe
  Megan Wachs authored Jul 14, 2020
  
  205b81fe
- Diplomacy: simplify information in package.scala · a389506b
  Megan Wachs authored Jul 13, 2020
  
  a389506b
- diplomacy: move scaladoc to package.scala · 70f90cd1
  Megan Wachs authored Jul 09, 2020
  
  70f90cd1
- update for review, rework on the ascii art of parameter propagation. · cf7b16ba
  Jiuyang liu authored Jul 09, 2020
  
  cf7b16ba
- wip documentation · 24c6758d
  Jiuyang liu authored Jul 06, 2020
  
  24c6758d
- Apply suggestions from code review · 9d052e61
  Megan Wachs authored Mar 11, 2020
```
Co-Authored-By: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Richard Xia <richardxia@richardxia.com>
```
  9d052e61
- WIP adding scaladoc comments for Diplomacy. · d61d6343
  Richard Xia authored Feb 27, 2020
  
  d61d6343
- add documentation to package · e7945d6b
  Jiuyang liu authored Mar 04, 2020
  
  e7945d6b
- split Nodes.scala from original PR. · 38b09902
  Jiuyang liu authored Feb 27, 2020
  
  38b09902
- Converted Vec to UInt in TLDebugModuleInner (#2597) · 375045a7
  Mathew T George authored Aug 22, 2020
```
Co-authored-by: Ernie Edgar <ernie.edgar@sifive.com>
```
  375045a7
Aug 21, 2020
- Merge pull request #2613 from chipsalliance/async-reset-trace-valid · ca7e5a4c
  Ernie Edgar authored Aug 20, 2020
```
Revise trace.valid gating method to relieve timing on reset
```
  ca7e5a4c
- Revise trace.valid gating method to relieve timing on reset · ede4d59a
  Ernie Edgar authored Aug 20, 2020
  
  ede4d59a
- Merge pull request #2595 from BrianGraysonSiV/add_tlb_params · 3b35ae9f
  Andrew Waterman authored Aug 20, 2020
```
Add params for nTLBBasePageSectors and nTLBSuperpages for both I and D TLBs
```
  3b35ae9f
Aug 20, 2020
- Merge pull request #2611 from chipsalliance/sync-to-async-rational-crossing · 9ceab5fa
  Ernie Edgar authored Aug 19, 2020
```
Change tile outputs to initialize with async reset
```
  9ceab5fa
Aug 19, 2020
- Ensure trace.valid is 0 during async reset · e3d506da
  Ernie Edgar authored Aug 19, 2020
  
  e3d506da
- Use unmodified, possibly async reset for notification ports · 16329253
  Ernie Edgar authored Aug 18, 2020
  
  16329253
- Ensure Sink does not act on input from Source before first clock edge · 7438f0be
  Ernie Edgar authored Aug 18, 2020
  
  7438f0be
Aug 17, 2020
- bug fix for ClockDivider · d06c9ee2
  Jiuyang Liu authored Aug 17, 2020
  
  d06c9ee2
Aug 15, 2020
- Merge pull request #2606 from chipsalliance/om-l2utlb · 105343ee
  John Ingalls authored Aug 14, 2020
```
Object Model: add L2 UTLB entries and memory
```
  105343ee
- Object Model: add UTLB entries and memory · 86dd97ec
  John Ingalls authored Aug 14, 2020
  
  86dd97ec
Aug 14, 2020
- Merge pull request #2577 from chipsalliance/nexusnode_debug · 6814964f
  Jiuyang Liu authored Aug 14, 2020
```
Add some debug info to diplomacy.
```
  6814964f
- fix words for reviewing. · 378c4442
  Jiuyang liu authored Aug 13, 2020
  
  378c4442
Aug 13, 2020
- update for review. · 0e5fbf61
  Jiuyang liu authored Aug 13, 2020
  
  0e5fbf61