Commits · bus-views · github.com / chipsalliance / rocket-chip

Nov 01, 2018
- subsystem: offer view from all bus wrappers · 2b801c32
  Henry Cook authored Oct 31, 2018
  
  2b801c32
- subsystem: optional devnulls in every bus wrapper · f1879b75
  Henry Cook authored Oct 31, 2018
  
  f1879b75
- subsystem: allow periphery bus to support wider atomics · 2620ba89
  Henry Cook authored Oct 31, 2018
  
  2620ba89
Oct 31, 2018
- Merge pull request #1680 from freechipsproject/clock-gate-disable · 4f9f3f4f
  Andrew Waterman authored Oct 30, 2018
```
Make clock_en_reg disappear when clockGate = false
```
  4f9f3f4f
- Allow subsytem w/ multiple cores and w/o PLIC (or external PLIC) (#1681) · 8f012cc6
  Alex Solomatnikov authored Oct 30, 2018
  
  8f012cc6
Oct 30, 2018
- Make RandomReplacement support non-power-of-2 values · 6e23d710
  Andrew Waterman authored Oct 29, 2018
  
  6e23d710
- Make clock_en_reg disappear when clockGate = false · f0e40a21
  Andrew Waterman authored Oct 29, 2018
  
  f0e40a21
- Merge pull request #1679 from freechipsproject/subsystem-bus-connectivity · 5439edc4
  Henry Cook authored Oct 29, 2018
```
Handle subsystem bus interconnectivity in child classes of BaseSubsystem pt 2
```
  5439edc4
- Merge pull request #1675 from freechipsproject/subsystem-bus-connectivity-2 · 183e937a
  Henry Cook authored Oct 29, 2018
```
Handle subsystem bus interconnectivity in child classes of BaseSubsystem
```
  183e937a
Oct 29, 2018
- subsystem: move inter-bus coupling to child classes of BaseSubsystem · 89ff3dc5
  Henry Cook authored Oct 26, 2018
  
  89ff3dc5
- subsystem: consolidate Fields and prune imports · f65bf821
  Henry Cook authored Oct 26, 2018
  
  f65bf821
- subsystem: streamline inter-bus couplers · 4a865f16
  Henry Cook authored Oct 26, 2018
  
  4a865f16
- groundtest: prune traits · 5d24a3e4
  Henry Cook authored Oct 26, 2018
  
  5d24a3e4
Oct 27, 2018
- Fix up(...).copy(...) use (#1677) · db3ee74e
  Alex Solomatnikov authored Oct 26, 2018
  
  db3ee74e
- Optimize away Fragmenter when minSize == maxSize (#1676) · 3afb34ae
  Alex Solomatnikov authored Oct 26, 2018
  
  3afb34ae
- Merge pull request #1674 from freechipsproject/subsystem-bus-connectivity · 35ea8e1a
  Henry Cook authored Oct 26, 2018
```
Move sbus.control_bus to subsystem level
```
  35ea8e1a
Oct 26, 2018
- subsystem: coherence manager coupler names · a1b5a44d
  Henry Cook authored Oct 25, 2018
  
  a1b5a44d
- config: put default error device on cbus · 6af27a60
  Henry Cook authored Oct 25, 2018
  
  6af27a60
- tilelink: avoid potential comb loop on ww bypass · 87205bb1
  Henry Cook authored Oct 25, 2018
  
  87205bb1
- tilelink: add wrapper-based factory methods for common adapters · 851efc2f
  Henry Cook authored Oct 23, 2018
  
  851efc2f
- subsystem: sbus.control_bus => cbus · d236de17
  Henry Cook authored Oct 23, 2018
  
  d236de17
Oct 25, 2018
- Add WidthWidget adapter to toTile (#1672) · 081caaab
  Ryan Macdonald authored Oct 24, 2018
  
  081caaab
Oct 24, 2018

Debug: Refactor how DMI/JTAG interfaces are paramterized (#1647) · efaefb24

Megan Wachs authored Oct 23, 2018

* Debug: Refactor how DMI/JTAG interfaces are paramterized

* Debug: pull out DTM instantiation code into a helper method

efaefb24

Oct 23, 2018
- Merge pull request #1673 from freechipsproject/pbus-adjustments · 9510d1c3
  Henry Cook authored Oct 22, 2018
```
Subsystem bus tweaks
```
  9510d1c3
- subsystem: PeripheryBus has built-in FifoFixer · d17899a2
  Henry Cook authored Oct 22, 2018
  
  d17899a2
- subsystem: remove some obviated vals · bdbe04ff
  Henry Cook authored Oct 17, 2018
  
  bdbe04ff
Oct 20, 2018
- Merge pull request #1670 from freechipsproject/bump-riscv-tools-for-pmp · b41ce1a2
  Srivatsa Yogendra authored Oct 19, 2018
```
bump riscv tools for spike change
```
  b41ce1a2
Oct 19, 2018
- bump riscv tools for spike change · cb67fb69
  Srivatsa Yogendra authored Oct 18, 2018
  
  cb67fb69
- Merge pull request #1666 from albertchen-sifive/expose-signals · bec31cea
  Alex Solomatnikov authored Oct 18, 2018
```
expose signals
```
  bec31cea
Oct 15, 2018
- travis: increase timeout for unit tests by 20 minutes (#1667) · b21c7879
  Wesley W. Terpstra authored Oct 14, 2018
  
  b21c7879
- Merge pull request #1664 from freechipsproject/banked-xbar · 20900383
  Wesley W. Terpstra authored Oct 14, 2018
```
Banked TileLink
```
  20900383
Oct 14, 2018
- Xbar: flip regionType check · 30b9de17
  Wesley W. Terpstra authored Oct 13, 2018
  
  30b9de17
Oct 13, 2018
- TLXbar: do not fanout or arbitrate cross-bank connections · 6db7c341
  Wesley W. Terpstra authored Oct 12, 2018
  
  6db7c341
- rocket: fix TinyConfig · 19f673c1
  Wesley W. Terpstra authored Oct 11, 2018
  
  19f673c1
Oct 12, 2018
- fix whitespace · 9d9da91e
  Abert Chen authored Oct 11, 2018
  
  9d9da91e
- make signals public · 36a59c4b
  Abert Chen authored Oct 11, 2018
  
  36a59c4b
Oct 11, 2018
- BankBinder: truncate transfer sizes at the banking granularity · 7e831c7c
  Wesley W. Terpstra authored Oct 10, 2018
```
Otherwise you could have a transfer that crosses between banks!
```
  7e831c7c
- subsystem: refactor membus to use new banking glue code · 060b264d
  Wesley W. Terpstra authored Oct 10, 2018
  
  060b264d
- ProbePicker: improve QoR in degenerate cases · d5abec10
  Wesley W. Terpstra authored Oct 10, 2018
  
  d5abec10
- ProbePicker: support banked caches with one tag bit · 31acc667
  Wesley W. Terpstra authored Oct 10, 2018
  
  31acc667