These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.

Fix IBuf bug

Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)

memgen: also randomize ren and rand register

Bump riscv-tools to bump riscv-tests for mi-csr test fix.

Bus blocker lock

Don't merge stores that manifest WAW hazards

Improve and use vlsi_mem_gen for verilator flow

The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.

tilelink: PMP controlled BusBlocker prevents bus accesses

Perform tag error detectoin/correction in same cycle as RAM

Don't report to the DTIM that data is cacheable

Otherwise, it will attempt to perform AMOs where they're unsupported!

The microarchitecture doesn't really support unified TLBs, so don't fake it.

The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.

Print out the compressed instruction when executing one

Revert "Remove one gate from D$ ECC check"

tilelink: allow insertion of TLDelayer on TLBus outward node

This reverts commit 7d94074b, which
works fine with optimistic behavioral RAMs but not real ones.

Fix ram model source reuse