* debug: Bump riscv-tools for riscv-tests timeout fix

* bump riscv-tools now that is merged into master

* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.

* cover: support covering cross-product of ready-valid

* tilelink: AsyncCrossing now has covers for all flow control logic

Bump riscv-tools.

Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.

Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.

* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup

Workaround: disable interrupts and then do:

.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i

Error support

From the AHB spec:
 "A slave only has to provide valid data when a transfer completes with an OKAY
  response. ERROR responses do not require valid read data."

We want each LFSR to generate independent noise.

diplomacy: switch adapter methods to node style

Fixes #1071

Better crossings deployed to bus and tile wrappers