Fix typos in Debug Module register descriptions.

Summary of changes:
* Fix := of DontCare to AsyncReset and Reset
* Boost performance of Vec cloning
* Add support for \t in printf
* Add ScalaDoc to RegNext

Add vector extension to OMISA

See https://github.com/riscv/riscv-v-spec/pull/351

Custommessage

* bump FIRRTL for async reset register fixes

* Bump firrtl to get verilog lint clean fix

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>

I$ accesses can be speculative, and raising the halt signal based
upon speculative accesses is problematic.

These errors can still be dealt with using a BusErrorUnit.

Correct link to diplomacy carvv paper.

Add IOHelper

#1969 accidentally reverted the fix implemented in #1934.

TLBs: make Entry classes available from other packages

Add feature-disable bit to suppress corrupt on GrantData

This isn't actually an RTL change, since Rocket unconditionally
provides the chicken CSR.

TLWidthWidget: one more fix for the port to chisel3

Improve D$ ECC timing

Temporarily suppressing corrupt GrantDatas facilitates using normal loads
and stores to wipe down uncorrectable errors.

Remove unused type parameter on RegisterRouter.

Convert some modules to Chisel3