Closes #1518

- don't supply a NullSource if there is no seip
- update comments

RoCC Build Fixes

This adds a build stage for checking that miscellaneous
configurations (like RoccExampleConfig) still compile. No tests are run.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

To avoid problems with inheritance/trait mix-in when building RoCC-enabled
configurations, this adds a new trait, HasFpuOpt, that declares the
optional FPU so that this exists before use in the implementation of lazy
RoCCs.

RoCC connection logic to the core is moved inside the implementation of
RocketTile so that the core is declared before it is used.

The RoCC cmd/resp routers are changed to be externally visible as
Option[T].

The type variable on HasLazyRoCCModule is removed as this was never used.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Allow PLIC to be optional

* DescribedSRAM

* add dts address anno

* optimized imports

It's no longer necessary (see https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
and removing it gets rid of a strange control path

L1D: update how corrupt responses are handled

Having both synchronous and asynchronous reporting mechanisms is confusing,
and the synchronous reporting isn't possible for some reasonable design
points, e.g., in-order processors with nonblocking caches.

Make sure to instantiate a bus-error unit if any TL slaves can error!

If the core tries to load from a corrupt block, it goes into a death spiral.
We need the BEU to be able to break us out of the load so it can be handled.

This is useful for test harness code.

I could have tried to implement real ECC like in TLRAM, but AXI4RAM is not
really intended to be used in synthesis, so this seems wasted effort.

Revert "Sram annos1 (#1490)"

This reverts commit 5d0e853e.

While the inversion trick works most of the time, if you are putting a
register in an FPGA IO buffer, you can't have any logic between the register
and the output pin.

Having a lot of children all called 'bridge' was not ideal.

Periphery clock changes

This reverts commit 5d0e853e.

Add DescribedSRAM

Dmi write delay fix

Add InModuleBody API