1. Mar 14, 2016
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  12. Jan 11, 2016
    • texane's avatar
      Merge pull request #363 from gingold-adacore/cache · 37ecabf7
      texane authored
      st-util: synchronize cache for stm32f7
      37ecabf7
    • Tristan Gingold's avatar
      st-util: synchronize cache for stm32f7 · 54c8d2ca
      Tristan Gingold authored
      This patch handles the cache on the cortex-m7 stm32f7 cpu.
      When gdb inserts a soft breakpoint (which is the default for
      code in RAM), it replaces an instruction with a breakpoint
      instruction.  But if the caches are enabled, the replacement
      may be made only in the D-cache.  To reach the I-cache, the
      D-cache must be flushed and the I-cache invalidated.
      
      This implementation is coarse: it cleans the whole D-cache
      and invalidate the whole I-cache.  It is possible to
      track which cache lines have to be cleaned and invalidated.
      54c8d2ca
  13. Dec 17, 2015