1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
|
(*=======================================================================================*)
(* RISCV Sail Model *)
(* *)
(* This Sail RISC-V architecture model, comprising all files and *)
(* directories except for the snapshots of the Lem and Sail libraries *)
(* in the prover_snapshots directory (which include copies of their *)
(* licences), is subject to the BSD two-clause licence below. *)
(* *)
(* Copyright (c) 2017-2023 *)
(* Prashanth Mundkur *)
(* Rishiyur S. Nikhil and Bluespec, Inc. *)
(* Jon French *)
(* Brian Campbell *)
(* Robert Norton-Wright *)
(* Alasdair Armstrong *)
(* Thomas Bauereiss *)
(* Shaked Flur *)
(* Christopher Pulte *)
(* Peter Sewell *)
(* Alexander Richardson *)
(* Hesham Almatary *)
(* Jessica Clarke *)
(* Microsoft, for contributions by Robert Norton-Wright and Nathaniel Wesley Filardo *)
(* Peter Rugg *)
(* Aril Computer Corp., for contributions by Scott Johnson *)
(* Philipp Tomsich *)
(* VRULL GmbH, for contributions by its employees *)
(* *)
(* All rights reserved. *)
(* *)
(* This software was developed by the above within the Rigorous *)
(* Engineering of Mainstream Systems (REMS) project, partly funded by *)
(* EPSRC grant EP/K008528/1, at the Universities of Cambridge and *)
(* Edinburgh. *)
(* *)
(* This software was developed by SRI International and the University of *)
(* Cambridge Computer Laboratory (Department of Computer Science and *)
(* Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and *)
(* under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA *)
(* SSITH research programme. *)
(* *)
(* This project has received funding from the European Research Council *)
(* (ERC) under the European Union’s Horizon 2020 research and innovation *)
(* programme (grant agreement 789108, ELVER). *)
(* *)
(* *)
(* Redistribution and use in source and binary forms, with or without *)
(* modification, are permitted provided that the following conditions *)
(* are met: *)
(* 1. Redistributions of source code must retain the above copyright *)
(* notice, this list of conditions and the following disclaimer. *)
(* 2. Redistributions in binary form must reproduce the above copyright *)
(* notice, this list of conditions and the following disclaimer in *)
(* the documentation and/or other materials provided with the *)
(* distribution. *)
(* *)
(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *)
(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *)
(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *)
(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *)
(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *)
(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *)
(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *)
(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *)
(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *)
(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *)
(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *)
(* SUCH DAMAGE. *)
(*=======================================================================================*)
open import Pervasives
open import Pervasives_extra
open import Sail2_instr_kinds
open import Sail2_values
open import Sail2_operators_mwords
open import Sail2_prompt_monad
open import Sail2_prompt
type bitvector = list Sail2_values.bitU
(* stub functions emulating the C softfloat interface *)
val softfloat_f16_round_to_int : bitvector -> bitvector -> bool -> unit
let softfloat_f16_round_to_int _ _ _ = ()
val softfloat_f32_round_to_int : bitvector -> bitvector -> bool -> unit
let softfloat_f32_round_to_int _ _ _ = ()
val softfloat_f64_round_to_int : bitvector -> bitvector -> bool -> unit
let softfloat_f64_round_to_int _ _ _ = ()
val softfloat_f16_add : bitvector -> bitvector -> bitvector -> unit
let softfloat_f16_add _ _ _ = ()
val softfloat_f16_sub : bitvector -> bitvector -> bitvector -> unit
let softfloat_f16_sub _ _ _ = ()
val softfloat_f16_mul : bitvector -> bitvector -> bitvector -> unit
let softfloat_f16_mul _ _ _ = ()
val softfloat_f16_div : bitvector -> bitvector -> bitvector -> unit
let softfloat_f16_div _ _ _ = ()
val softfloat_f32_add : bitvector -> bitvector -> bitvector -> unit
let softfloat_f32_add _ _ _ = ()
val softfloat_f32_sub : bitvector -> bitvector -> bitvector -> unit
let softfloat_f32_sub _ _ _ = ()
val softfloat_f32_mul : bitvector -> bitvector -> bitvector -> unit
let softfloat_f32_mul _ _ _ = ()
val softfloat_f32_div : bitvector -> bitvector -> bitvector -> unit
let softfloat_f32_div _ _ _ = ()
val softfloat_f64_add : bitvector -> bitvector -> bitvector -> unit
let softfloat_f64_add _ _ _ = ()
val softfloat_f64_sub : bitvector -> bitvector -> bitvector -> unit
let softfloat_f64_sub _ _ _ = ()
val softfloat_f64_mul : bitvector -> bitvector -> bitvector -> unit
let softfloat_f64_mul _ _ _ = ()
val softfloat_f64_div : bitvector -> bitvector -> bitvector -> unit
let softfloat_f64_div _ _ _ = ()
val softfloat_f16_muladd : bitvector -> bitvector -> bitvector -> bitvector -> unit
let softfloat_f16_muladd _ _ _ _ = ()
val softfloat_f32_muladd : bitvector -> bitvector -> bitvector -> bitvector -> unit
let softfloat_f32_muladd _ _ _ _ = ()
val softfloat_f64_muladd : bitvector -> bitvector -> bitvector -> bitvector -> unit
let softfloat_f64_muladd _ _ _ _ = ()
val softfloat_f16_sqrt : bitvector -> bitvector -> unit
let softfloat_f16_sqrt _ _ = ()
val softfloat_f32_sqrt : bitvector -> bitvector -> unit
let softfloat_f32_sqrt _ _ = ()
val softfloat_f64_sqrt : bitvector -> bitvector -> unit
let softfloat_f64_sqrt _ _ = ()
val softfloat_f16_to_i32: bitvector -> bitvector -> unit
let softfloat_f16_to_i32 _ _ = ()
val softfloat_f16_to_ui32: bitvector -> bitvector -> unit
let softfloat_f16_to_ui32 _ _ = ()
val softfloat_i32_to_f16: bitvector -> bitvector -> unit
let softfloat_i32_to_f16 _ _ = ()
val softfloat_ui32_to_f16: bitvector -> bitvector -> unit
let softfloat_ui32_to_f16 _ _ = ()
val softfloat_f16_to_i64: bitvector -> bitvector -> unit
let softfloat_f16_to_i64 _ _ = ()
val softfloat_f16_to_ui64: bitvector -> bitvector -> unit
let softfloat_f16_to_ui64 _ _ = ()
val softfloat_i64_to_f16: bitvector -> bitvector -> unit
let softfloat_i64_to_f16 _ _ = ()
val softfloat_ui64_to_f16: bitvector -> bitvector -> unit
let softfloat_ui64_to_f16 _ _ = ()
val softfloat_f32_to_i32: bitvector -> bitvector -> unit
let softfloat_f32_to_i32 _ _ = ()
val softfloat_f32_to_ui32: bitvector -> bitvector -> unit
let softfloat_f32_to_ui32 _ _ = ()
val softfloat_i32_to_f32: bitvector -> bitvector -> unit
let softfloat_i32_to_f32 _ _ = ()
val softfloat_ui32_to_f32: bitvector -> bitvector -> unit
let softfloat_ui32_to_f32 _ _ = ()
val softfloat_f32_to_i64: bitvector -> bitvector -> unit
let softfloat_f32_to_i64 _ _ = ()
val softfloat_f32_to_ui64: bitvector -> bitvector -> unit
let softfloat_f32_to_ui64 _ _ = ()
val softfloat_i64_to_f32: bitvector -> bitvector -> unit
let softfloat_i64_to_f32 _ _ = ()
val softfloat_ui64_to_f32: bitvector -> bitvector -> unit
let softfloat_ui64_to_f32 _ _ = ()
val softfloat_f64_to_i32: bitvector -> bitvector -> unit
let softfloat_f64_to_i32 _ _ = ()
val softfloat_f64_to_ui32: bitvector -> bitvector -> unit
let softfloat_f64_to_ui32 _ _ = ()
val softfloat_i32_to_f64: bitvector -> bitvector -> unit
let softfloat_i32_to_f64 _ _ = ()
val softfloat_ui32_to_f64: bitvector -> bitvector -> unit
let softfloat_ui32_to_f64 _ _ = ()
val softfloat_f64_to_i64: bitvector -> bitvector -> unit
let softfloat_f64_to_i64 _ _ = ()
val softfloat_f64_to_ui64: bitvector -> bitvector -> unit
let softfloat_f64_to_ui64 _ _ = ()
val softfloat_i64_to_f64: bitvector -> bitvector -> unit
let softfloat_i64_to_f64 _ _ = ()
val softfloat_ui64_to_f64: bitvector -> bitvector -> unit
let softfloat_ui64_to_f64 _ _ = ()
val softfloat_f16_to_f32: bitvector -> bitvector -> unit
let softfloat_f16_to_f32 _ _ = ()
val softfloat_f16_to_f64: bitvector -> bitvector -> unit
let softfloat_f16_to_f64 _ _ = ()
val softfloat_f32_to_f64: bitvector -> bitvector -> unit
let softfloat_f32_to_f64 _ _ = ()
val softfloat_f32_to_f16: bitvector -> bitvector -> unit
let softfloat_f32_to_f16 _ _ = ()
val softfloat_f64_to_f16: bitvector -> bitvector -> unit
let softfloat_f64_to_f16 _ _ = ()
val softfloat_f64_to_f32: bitvector -> bitvector -> unit
let softfloat_f64_to_f32 _ _ = ()
val softfloat_f16_lt : bitvector -> bitvector -> unit
let softfloat_f16_lt _ _ = ()
val softfloat_f16_lt_quiet : bitvector -> bitvector -> unit
let softfloat_f16_lt_quiet _ _ = ()
val softfloat_f16_le : bitvector -> bitvector -> unit
let softfloat_f16_le _ _ = ()
val softfloat_f16_le_quiet : bitvector -> bitvector -> unit
let softfloat_f16_le_quiet _ _ = ()
val softfloat_f16_eq : bitvector -> bitvector -> unit
let softfloat_f16_eq _ _ = ()
val softfloat_f32_lt : bitvector -> bitvector -> unit
let softfloat_f32_lt _ _ = ()
val softfloat_f32_lt_quiet : bitvector -> bitvector -> unit
let softfloat_f32_lt_quiet _ _ = ()
val softfloat_f32_le : bitvector -> bitvector -> unit
let softfloat_f32_le _ _ = ()
val softfloat_f32_le_quiet : bitvector -> bitvector -> unit
let softfloat_f32_le_quiet _ _ = ()
val softfloat_f32_eq : bitvector -> bitvector -> unit
let softfloat_f32_eq _ _ = ()
val softfloat_f64_lt : bitvector -> bitvector -> unit
let softfloat_f64_lt _ _ = ()
val softfloat_f64_lt_quiet : bitvector -> bitvector -> unit
let softfloat_f64_lt_quiet _ _ = ()
val softfloat_f64_le : bitvector -> bitvector -> unit
let softfloat_f64_le _ _ = ()
val softfloat_f64_le_quiet : bitvector -> bitvector -> unit
let softfloat_f64_le_quiet _ _ = ()
val softfloat_f64_eq : bitvector -> bitvector -> unit
let softfloat_f64_eq _ _ = ()
|
