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AgeCommit message (Expand)AuthorFilesLines
2018-12-22Fixed fence.tsoShaked Flur1-1/+1
2018-12-22When speculate_conditional fails we still need to write 0b1 to rd;Shaked Flur1-8/+13
2018-12-20Address the fixme for rmem integration of LR as suggested by Shaked.Prashanth Mundkur1-44/+44
2018-12-20Add fence.tso.Prashanth Mundkur1-0/+18
2018-11-29RISC-V: implement WFI in the platform model.Prashanth Mundkur1-2/+2
2018-11-29RISC-V: factor the execution trace.Prashanth Mundkur1-2/+2
2018-11-29RISC-V: no ldu for rv64iBrian Campbell1-3/+3
2018-11-29RISC-V: add some missing constraints on compressed instruction encodingsBrian Campbell1-3/+3
2018-11-29RISC-V: add checks for misaligned targets to jumps and branchesBrian Campbell1-7/+19
2018-11-09RISC-V: add missed c.ebreak instructionPrashanth Mundkur1-0/+10
2018-11-07RISC-V: fix assembly mappings for lr/sc.Prashanth Mundkur1-2/+2
2018-10-23RISC-V: separate jalr execute clause for seq model and rmem.Prashanth Mundkur1-16/+2
2018-10-23RISC-V: Initial splitting of instructions across multiple files.Prashanth Mundkur1-37/+0
2018-10-23RISC-V: various fixesPrashanth Mundkur1-2/+2
2018-10-05RISC-V: encode/decode and assembly mappings for compressed instructionsJon French1-188/+91
2018-08-28fix bug in RISCV assembly mapping, incorrect order of FENCE pred/succ bitsJon French1-1/+1
2018-07-27Add some missing rv64i instructions, discovered when annotating the riscv isa...Prashanth Mundkur1-0/+27
2018-07-20Add assorted comments, consistency fixes and cleanup.Prashanth Mundkur1-337/+310
2018-07-12Fixed a nested comment issueShaked Flur1-1/+1
2018-07-11Add fixme note about riscv jalr.Prashanth Mundkur1-0/+8
2018-07-11Update the exception code for riscv LR after clarification on isa-dev.Prashanth Mundkur1-1/+4
2018-07-11RISC-V model fixes for RMEMJon French1-7/+11
2018-07-10correct pretty-printing using mappingsJon French1-192/+4
2018-07-09Support writes to misa.C in riscv.Prashanth Mundkur1-2/+2
2018-07-08Move the riscv analysis function into its own file for coverage purposes.Prashanth Mundkur1-183/+0
2018-07-07Cancel riscv reservation before i/o scheduling, tweak reservation tracing.Prashanth Mundkur1-4/+2
2018-07-07An initial fix to riscv lr/sc, needs a review.Prashanth Mundkur1-37/+80
2018-07-05Fix printing of aq/rl flags in risc-v lr/sc.Prashanth Mundkur1-16/+22
2018-07-05support acquire/release loads/stores in RISCV initial_analysisJon French1-4/+4
2018-07-05restore missing RISC-V fence types in sail2; ignore io bits in fences more cl...Jon French1-32/+23
2018-06-28further changes to support rmemJon French1-34/+60
2018-06-25Add a riscv platform parameter to control trapping to M-mode on misaligned ac...Prashanth Mundkur1-2/+15
2018-06-25Hook in the missed misa legalizer.Prashanth Mundkur1-0/+1
2018-06-25Fix a missed fixme for the sstatus view of mstatus.Prashanth Mundkur1-1/+1
2018-06-22More trace log tweaks.Prashanth Mundkur1-0/+4
2018-06-21add PMP registers to CSR, fix buildJon French1-12/+17
2018-06-21changes to riscv model to support rmemJon French1-0/+195
2018-06-11Update retire semantics for riscv WFI.Prashanth Mundkur1-10/+7
2018-06-11Merge branch 'sail2' into mappingsJon French1-74/+126
2018-06-11change double-caret for string-append-pattern to single caret, since that wou...Jon French1-27/+27
2018-06-11drop now-unnecessary type annotation clutter from riscv decode mappingsJon French1-42/+55
2018-06-09Increment minstret on instruction retires, and handle the case when the minst...Prashanth Mundkur1-73/+121
2018-06-09Some fixes to counteren handling.Prashanth Mundkur1-4/+4
2018-06-08Add counteren registers.Prashanth Mundkur1-0/+4
2018-06-08type checking mappings: allow inferring based on the other side's id inferencesJon French1-2/+2
2018-05-23riscv decode now uses mapping-decode and passes testsJon French1-168/+57
2018-05-21further RISCV mapping: all extant non-compressed instructions doneJon French1-1/+185
2018-05-18more riscv mappingJon French1-19/+25
2018-05-18more riscv mappings; riscv now builds successfully to lem which builds to isa...Jon French1-37/+74
2018-05-15Merge branch 'sail2' into mappingsJon French1-1/+2
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