sail-riscv.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-09-04	Merge remote-tracking branch 'origin/master' into vmem_ext.vmem_ext	Robert Norton	1	-1/+1
2019-08-19	RISC-V spec, without implicit casts	Alasdair Armstrong	1	-1/+1
2019-08-09	Allow accumulation of information during page-table-walk for extensions.	Prashanth Mundkur	1	-32/+29
2019-07-22	Make a custom exception code available for extensions, and remove the E_CHERI...	Prashanth Mundkur	1	-50/+57
2019-07-16	Use reserved bits in PTEs for vmem extensions on RV64, as allowed by the spec...	Prashanth Mundkur	1	-8/+12
2019-07-15	Allow extensions to types of memory access, and factor out PTE and PTW defini...	Prashanth Mundkur	1	-2/+2
2019-06-24	Add PMP checks to physical memory accesses.	Prashanth Mundkur	1	-1/+1
2019-06-24	Narrow the external interface to riscv_mem to mem_{read,write,write_ea}.	Prashanth Mundkur	1	-3/+3
2019-06-24	Starting cleaning up physical memory bits for pmp integration.	Prashanth Mundkur	1	-3/+2
2019-04-24	Add extended model from cheri-merge.	Prashanth Mundkur	1	-3/+3
2019-03-11	Fixes for Sv39 TLB.	Prashanth Mundkur	1	-0/+5
2019-03-08	Initial attempt at genericizing TLB entries, and re-introduce for Sv39.	Prashanth Mundkur	1	-24/+92
2019-02-22	Fix address translation bug in ordering of width-extension and shift in pte. ...	Prashanth Mundkur	1	-1/+1
2019-02-13	Add Sv32 and Sv48 by essentially copying Sv39.	Prashanth Mundkur	1	-1/+0
2019-02-13	Remove the use of the TLB until it is more generic across the various archite...	Prashanth Mundkur	1	-56/+24
2019-02-13	Pull out the Sv39 and its TLB into separate files.	Prashanth Mundkur	1	-0/+139