| Age | Commit message (Collapse) | Author | Files | Lines |
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These guards were missing from one side of each clause.
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This script was used to do the modification:
```
from pathlib import Path
import re
RE_LINE = r"/\*={50,150}\*/\n"
RE_MIDDLE = r"/\*.*\*/\n"
NEW_TEXT = """/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/
"""
REPLACEMENT = re.compile(rf"^{RE_LINE}(?:{RE_MIDDLE}){{10,100}}{RE_LINE}")
def main():
for file in Path("model").glob("**/*.sail"):
text = file.read_text(encoding="utf-8")
text = REPLACEMENT.sub(NEW_TEXT, text, 1)
file.write_text(text, encoding="utf-8")
if __name__ == "__main__":
main()
```
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There are a few places where operand/field names are not consistent
across scattered definitions for an instruction.
Here, parameter `rs2` is used for encode/decode and execute, but
`rd` is used for the same purpose in the assembly clause:
```
mapping clause encdec_compressed = C_SWSP(ui76 @ ui52, rs2)
<-> 0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10
function clause execute (C_SWSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
execute(STORE(imm, rs2, sp, WORD, false, false))
}
mapping clause assembly = C_SWSP(uimm, rd)
<-> "c.swsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)
```
Fix these by using the operand names found in
"The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA",
document version 20191213, and "RISC-V Cryptography Extensions
Volumn I: Scalar & Entropy Source Instructions", version v1.0.1.
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Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
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This strips trailing whitespace and fixes line endings. I had to add the
*.dump files to the exclude list to avoid excessive changes, but
ideally these would not be part of the repository since they can just be
generated by running objdump manually.
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Trying to make the behavior of aesks1i easier to understand, and more
obviously correspond to the specification.
- Ensure that the aes_decode_rcon function only accepts valid values, plus
add comments.
- Re-name operands to aesks1i rcon -> rnum to be in line with the specification
- Re-structure the Sail code for clarity based on jrtc27's suggestion.
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Remove weird whitespace " );" -> ");" at end of expressions to be
consistent with the rest of the code base.
On branch scalar-crypto-tidy
Changes to be committed:
modified: model/riscv_insts_zkn.sail
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Add spaces pre/post used of "==" operator to be consistent with the rest
of the code.
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Merged scalar-crypto pull request #99 of 1.0.0-rc2 spec work from Ben Marshall. See https://github.com/riscv/sail-riscv/pull/99.
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