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riscv_insts_zicsr.sail
Age
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Author
Files
Lines
2019-07-09
Add some missed logging guards.
Prashanth Mundkur
1
-2
/
+4
2019-06-28
Avoid implicit casts to string
Alasdair
1
-2
/
+2
2019-06-27
Fix the lem target.
Prashanth Mundkur
1
-20
/
+8
2019-06-21
Checked locked flag on PMP reg writes, and add the special case for the pmpad...
Prashanth Mundkur
1
-16
/
+16
2019-06-20
Hook in csr reads/writes to PMP regs. Locked entries are not yet handled.
Prashanth Mundkur
1
-3
/
+54
2019-05-14
Improve the interface to access CSRs in extensions.
Prashanth Mundkur
1
-2
/
+2
2019-05-10
Rename regbits to regidx, to clarify the type is an index and not the content...
Prashanth Mundkur
1
-1
/
+1
2019-05-10
Use an explicit enum to indicate the retire status as opposed to a boolean to...
Prashanth Mundkur
1
-2
/
+2
2019-05-07
Allow overrides for mtvec/stvec accessors.
Prashanth Mundkur
1
-4
/
+4
2019-04-24
Add extended model from cheri-merge.
Prashanth Mundkur
1
-4
/
+4
2019-02-19
Use sizeof xlen instead of the value definitions of xlen.
Prashanth Mundkur
1
-9
/
+9
2019-02-15
Define counter CSRs, and guard accesses from RV32.
Prashanth Mundkur
1
-85
/
+95
2019-02-12
Start extracting bits of vmem that should be common to RV32, and add some def...
Prashanth Mundkur
1
-4
/
+1
2019-02-11
Fix mvendorid width.
Prashanth Mundkur
1
-1
/
+1
2019-01-29
Add CSRs for the 'N' extension arch state and expose to CSR read/write.
Prashanth Mundkur
1
-3
/
+11
2019-01-25
Factor out each extension into separate files, do some minor cleanup.
Prashanth Mundkur
1
-0
/
+159