aboutsummaryrefslogtreecommitdiff
path: root/model/riscv_insts_aext.sail
AgeCommit message (Collapse)AuthorFilesLines
2019-06-24Add PMP checks to physical memory accesses.Prashanth Mundkur1-10/+11
- unify AccessType and ReadType since they were essentially redundant, making it easier to implement PMP checks for ReadWrite/atomic accesses. - add command line options to enable PMP in the platform - also fix the matching for the case when all entries are off
2019-06-24Narrow the external interface to riscv_mem to mem_{read,write,write_ea}.Prashanth Mundkur1-4/+4
2019-05-23Be more careful about matching only instructions that are defined for xlen ↵Robert Norton1-6/+6
being built.
2019-05-10Rename regbits to regidx, to clarify the type is an index and not the ↵Prashanth Mundkur1-4/+4
contents of a register.
2019-05-10Use an explicit enum to indicate the retire status as opposed to a boolean ↵Prashanth Mundkur1-24/+24
to improve clarity.
2019-05-02Push address calculation inside the data_check_addr hook and rename it to ↵rmn30Robert Norton1-9/+12
data_get_addr. This avoids a double register read in CHERI case.
2019-05-01Add base address register as extra argument to ext_data_check_addr hook to ↵Robert Norton1-3/+3
assist with implementing CHERI capability mode.
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur1-105/+123
2019-03-06Fix a missed case of reservation cancellation.Prashanth Mundkur1-1/+1
2019-02-19Use sizeof xlen instead of the value definitions of xlen.Prashanth Mundkur1-10/+10
2019-02-15More RV32 fixes.Prashanth Mundkur1-5/+7
2019-02-15Add xlen guards on double-word operations to make them RV64-only.Prashanth Mundkur1-26/+26
2019-02-06Fix register rs2 read in AMO.Prashanth Mundkur1-1/+1
2019-01-25Add misa checks for instructions not in the base set.Prashanth Mundkur1-109/+124
2019-01-25Factor out each extension into separate files, do some minor cleanup.Prashanth Mundkur1-0/+230