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This script was used to do the modification:
```
from pathlib import Path
import re
RE_LINE = r"/\*={50,150}\*/\n"
RE_MIDDLE = r"/\*.*\*/\n"
NEW_TEXT = """/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/
"""
REPLACEMENT = re.compile(rf"^{RE_LINE}(?:{RE_MIDDLE}){{10,100}}{RE_LINE}")
def main():
for file in Path("model").glob("**/*.sail"):
text = file.read_text(encoding="utf-8")
text = REPLACEMENT.sub(NEW_TEXT, text, 1)
file.write_text(text, encoding="utf-8")
if __name__ == "__main__":
main()
```
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Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
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I plan to change sail to allow this by always topologically sorting
after descattering, as it seems nicer to allow these enums to be
declared where they are used, but until then this should unblock us from
making progress.
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>----------------
Modified existing file: riscv_sys_regs.sail
Added predicates 'haveFExt()' and 'haveDExt()'
Similar to existing 'haveNExt()', 'haveAtomics()', etc.
>----------------
New files: riscv_flen_F.sail and riscv_flen_D.sail
These are analogous to existing: riscv_xlen32.sail and riscv_xlen64.sail
>----------------
New file: riscv_freg_type.sail
This is analogous to existing: riscv_reg_type.sail
>----------------
New file: riscv_fdext_regs.sail
This is the definition of the floating-point reg file, analogous to
existing: riscv_regs.sail
>----------------
New file: riscv_insts_fdext.sail
This is the spec of F and D instructions.
The file has a section separated by /* **** */ lines
for each related group of instructions.
Each section contains:
union clause ast ...
mapping clause encdec ...
function clause execute ...
mapping clause assembly ...
Finished all the ast, encdec, and assembly sections.
For the execute sections:
- Finished LOAD_FP and STORE_FP
- For FADD_S/FSUB_S/FMUL_S/FDIV_S: done, assuming certain primitives
for the actual arithmetic, which have to be linked into Berkeley
softloat.
- Rest of them have placeholders that treat them as illegal instrs.
Todo:
- Finish 'function clause execute' for remaining instructions,
and collect list of primitives needed (based on softfloat)
- Fix up Makefile to include these new files, make sure everything compiles.
- Connect softfloat, and run ISA tests.
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