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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-11-25 10:56:18 -0800
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-11-25 10:56:33 -0800
commita3e02531b8dec1201800e059a071e02f8bdddcee (patch)
tree5e082ddb7643b163fe7fe2fa0fc9551f259666e0 /model/riscv_freg_type.sail
parenta9a0002c540e33611975928d9a2ff7703f4674e6 (diff)
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Add the missing fcvt.{ds}.{sd} instructions.
Diffstat (limited to 'model/riscv_freg_type.sail')
-rw-r--r--model/riscv_freg_type.sail1
1 files changed, 1 insertions, 0 deletions
diff --git a/model/riscv_freg_type.sail b/model/riscv_freg_type.sail
index e56377c..3b099db 100644
--- a/model/riscv_freg_type.sail
+++ b/model/riscv_freg_type.sail
@@ -43,6 +43,7 @@ enum f_madd_op_D = {FMADD_D, FMSUB_D, FNMSUB_D, FNMADD_D}
enum f_bin_rm_op_D = {FADD_D, FSUB_D, FMUL_D, FDIV_D}
enum f_un_rm_op_D = {FSQRT_D, FCVT_W_D, FCVT_WU_D, FCVT_D_W, FCVT_D_WU, // RV32 and RV64
+ FCVT_S_D, FCVT_D_S,
FCVT_L_D, FCVT_LU_D, FCVT_D_L, FCVT_D_LU} // RV64 only
enum f_bin_op_D = {FSGNJ_D, FSGNJN_D, FSGNJX_D, FMIN_D, FMAX_D, FEQ_D, FLT_D, FLE_D}