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2025-12-22Improved clang-format style (#1396)Tim Hutt1-37/+19
This fixes various annoyances in our clang-format style that have been bothering me for a while: * Binpacking arguments/parameters and aligning them to the opening `(` is *really* bad for diffs/conflict resolution. This changes it to try to match the "prettier" algorithm (also used by Sail's autoformatter), which has much simpler and better behaviour - if the arguments fit on one line do that, otherwise put each argument on its own line. * Don't put functions on one line. This is also a little diff-unfriendly and feels unnecessarily inconsistent to me. * The line length limit of 80 characters is very constrictive so I increased it to 120 characters. * For some reason it didn't put `{` on a new line... except for function bodies, which is weirdly inconsistent. Now `{` never starts on a new line. * Sort `#include`s. This might have been needed in the past but I verified it builds with sorted includes now.
2025-08-20Load ELFs via ELFIO and add symbols to the trace output (#1177)Tim Hutt1-0/+106
Add ELFIO dependency and use it to load ELFs into memory instead of using Sail's built-in ELF support. This gives us greater control, e.g. it will allow supporting position independent ELFs in future. It also allows printing symbols in the log, which is implemented here. Example output: ``` $ c_emulator/sail_riscv_sim test/2025-07-16/riscv-tests/rv64mi-p-breakpoint --trace-instr ELF Entry @ 0x80000000 HTIF located at 0x80001000 begin_signature: 0x80002000 end_signature: 0x80002010 [0] [M]: 0x0000000000001000 (0x00000297) auipc x5, 0x0 [1] [M]: 0x0000000000001004 (0x02028593) addi x11, x5, 0x20 [2] [M]: 0x0000000000001008 (0xF1402573) csrrs x10, mhartid, x0 [3] [M]: 0x000000000000100C (0x0182B283) ld x5, 0x18(x5) [4] [M]: 0x0000000000001010 (0x00028067) jalr x0, 0x0(x5) [5] [M]: 0x0000000080000000 (0x0540006F) jal x0, 0x54 _start+0 [6] [M]: 0x0000000080000054 (0x00000093) addi x1, x0, 0x0 reset_vector+0 [7] [M]: 0x0000000080000058 (0x00000113) addi x2, x0, 0x0 reset_vector+4 [8] [M]: 0x000000008000005C (0x00000193) addi x3, x0, 0x0 reset_vector+8 [9] [M]: 0x0000000080000060 (0x00000213) addi x4, x0, 0x0 reset_vector+12 [10] [M]: 0x0000000080000064 (0x00000293) addi x5, x0, 0x0 reset_vector+16 [11] [M]: 0x0000000080000068 (0x00000313) addi x6, x0, 0x0 reset_vector+20 [12] [M]: 0x000000008000006C (0x00000393) addi x7, x0, 0x0 reset_vector+24 [13] [M]: 0x0000000080000070 (0x00000413) addi x8, x0, 0x0 reset_vector+28 [14] [M]: 0x0000000080000074 (0x00000493) addi x9, x0, 0x0 reset_vector+32 [15] [M]: 0x0000000080000078 (0x00000513) addi x10, x0, 0x0 reset_vector+36 [16] [M]: 0x000000008000007C (0x00000593) addi x11, x0, 0x0 reset_vector+40 [17] [M]: 0x0000000080000080 (0x00000613) addi x12, x0, 0x0 reset_vector+44 [18] [M]: 0x0000000080000084 (0x00000693) addi x13, x0, 0x0 reset_vector+48 [19] [M]: 0x0000000080000088 (0x00000713) addi x14, x0, 0x0 reset_vector+52 [20] [M]: 0x000000008000008C (0x00000793) addi x15, x0, 0x0 reset_vector+56 [21] [M]: 0x0000000080000090 (0x00000813) addi x16, x0, 0x0 reset_vector+60 [22] [M]: 0x0000000080000094 (0x00000893) addi x17, x0, 0x0 reset_vector+64 [23] [M]: 0x0000000080000098 (0x00000913) addi x18, x0, 0x0 reset_vector+68 [24] [M]: 0x000000008000009C (0x00000993) addi x19, x0, 0x0 reset_vector+72 [25] [M]: 0x00000000800000A0 (0x00000A13) addi x20, x0, 0x0 reset_vector+76 [26] [M]: 0x00000000800000A4 (0x00000A93) addi x21, x0, 0x0 reset_vector+80 [27] [M]: 0x00000000800000A8 (0x00000B13) addi x22, x0, 0x0 reset_vector+84 [28] [M]: 0x00000000800000AC (0x00000B93) addi x23, x0, 0x0 reset_vector+88 [29] [M]: 0x00000000800000B0 (0x00000C13) addi x24, x0, 0x0 reset_vector+92 [30] [M]: 0x00000000800000B4 (0x00000C93) addi x25, x0, 0x0 reset_vector+96 [31] [M]: 0x00000000800000B8 (0x00000D13) addi x26, x0, 0x0 reset_vector+100 [32] [M]: 0x00000000800000BC (0x00000D93) addi x27, x0, 0x0 reset_vector+104 [33] [M]: 0x00000000800000C0 (0x00000E13) addi x28, x0, 0x0 reset_vector+108 [34] [M]: 0x00000000800000C4 (0x00000E93) addi x29, x0, 0x0 reset_vector+112 [35] [M]: 0x00000000800000C8 (0x00000F13) addi x30, x0, 0x0 reset_vector+116 [36] [M]: 0x00000000800000CC (0x00000F93) addi x31, x0, 0x0 reset_vector+120 [37] [M]: 0x00000000800000D0 (0xF1402573) csrrs x10, mhartid, x0 reset_vector+124 [38] [M]: 0x00000000800000D4 (0x00051063) bne x10, x0, 0x0 reset_vector+128 [39] [M]: 0x00000000800000D8 (0x00000297) auipc x5, 0x0 reset_vector+132 [40] [M]: 0x00000000800000DC (0x01028293) addi x5, x5, 0x10 reset_vector+136 [41] [M]: 0x00000000800000E0 (0x30529073) csrrw x0, mtvec, x5 reset_vector+140 [42] [M]: 0x00000000800000E4 (0x74445073) csrrwi x0, 0x744, 0x8 reset_vector+144 [43] [M]: 0x00000000800000E8 (0x00000297) auipc x5, 0x0 reset_vector+148 [44] [M]: 0x00000000800000EC (0x01028293) addi x5, x5, 0x10 reset_vector+152 [45] [M]: 0x00000000800000F0 (0x30529073) csrrw x0, mtvec, x5 reset_vector+156 [46] [M]: 0x00000000800000F4 (0x18005073) csrrwi x0, satp, 0x0 reset_vector+160 [47] [M]: 0x00000000800000F8 (0x00000297) auipc x5, 0x0 reset_vector+164 [48] [M]: 0x00000000800000FC (0x02428293) addi x5, x5, 0x24 reset_vector+168 [49] [M]: 0x0000000080000100 (0x30529073) csrrw x0, mtvec, x5 reset_vector+172 [50] [M]: 0x0000000080000104 (0x0010029B) addiw x5, x0, 0x1 reset_vector+176 [51] [M]: 0x0000000080000108 (0x03529293) slli x5, x5, 0x35 reset_vector+180 [52] [M]: 0x000000008000010C (0xFFF28293) addi x5, x5, -0x1 reset_vector+184 [53] [M]: 0x0000000080000110 (0x3B029073) csrrw x0, pmpaddr0, x5 reset_vector+188 [54] [M]: 0x0000000080000114 (0x01F00293) addi x5, x0, 0x1f reset_vector+192 [55] [M]: 0x0000000080000118 (0x3A029073) csrrw x0, pmpcfg0, x5 reset_vector+196 [56] [M]: 0x000000008000011C (0x30405073) csrrwi x0, mie, 0x0 reset_vector+200 [57] [M]: 0x0000000080000120 (0x00000297) auipc x5, 0x0 reset_vector+204 [58] [M]: 0x0000000080000124 (0x01428293) addi x5, x5, 0x14 reset_vector+208 [59] [M]: 0x0000000080000128 (0x30529073) csrrw x0, mtvec, x5 reset_vector+212 [60] [M]: 0x000000008000012C (0x30205073) csrrwi x0, medeleg, 0x0 reset_vector+216 [61] [M]: 0x0000000080000130 (0x30305073) csrrwi x0, mideleg, 0x0 reset_vector+220 [62] [M]: 0x0000000080000134 (0x00000193) addi x3, x0, 0x0 reset_vector+224 [63] [M]: 0x0000000080000138 (0x00000297) auipc x5, 0x0 reset_vector+228 [64] [M]: 0x000000008000013C (0xECC28293) addi x5, x5, -0x134 reset_vector+232 [65] [M]: 0x0000000080000140 (0x30529073) csrrw x0, mtvec, x5 reset_vector+236 [66] [M]: 0x0000000080000144 (0x00100513) addi x10, x0, 0x1 reset_vector+240 [67] [M]: 0x0000000080000148 (0x01F51513) slli x10, x10, 0x1f reset_vector+244 [68] [M]: 0x000000008000014C (0x00055C63) bge x10, x0, 0x18 reset_vector+248 [69] [M]: 0x0000000080000164 (0x00000293) addi x5, x0, 0x0 reset_vector+272 [70] [M]: 0x0000000080000168 (0x00028A63) beq x5, x0, 0x14 reset_vector+276 [71] [M]: 0x000000008000017C (0x30005073) csrrwi x0, mstatus, 0x0 reset_vector+296 [72] [M]: 0x0000000080000180 (0x00002537) lui x10, 0x2 reset_vector+300 [73] [M]: 0x0000000080000184 (0x8005051B) addiw x10, x10, -0x800 reset_vector+304 [74] [M]: 0x0000000080000188 (0x30052073) csrrs x0, mstatus, x10 reset_vector+308 [75] [M]: 0x000000008000018C (0x00000297) auipc x5, 0x0 reset_vector+312 [76] [M]: 0x0000000080000190 (0x01428293) addi x5, x5, 0x14 reset_vector+316 [77] [M]: 0x0000000080000194 (0x34129073) csrrw x0, mepc, x5 reset_vector+320 [78] [M]: 0x0000000080000198 (0xF1402573) csrrs x10, mhartid, x0 reset_vector+324 [79] [M]: 0x000000008000019C (0x30200073) mret reset_vector+328 [80] [M]: 0x00000000800001A0 (0x00200193) addi x3, x0, 0x2 reset_vector+332 [81] [M]: 0x00000000800001A4 (0x00000517) auipc x10, 0x0 reset_vector+336 [82] [M]: 0x00000000800001A8 (0x01450513) addi x10, x10, 0x14 reset_vector+340 [83] [M]: 0x00000000800001AC (0x30551573) csrrw x10, mtvec, x10 reset_vector+344 [84] [M]: 0x00000000800001B0 (0x00800593) addi x11, x0, 0x8 reset_vector+348 [85] [M]: 0x00000000800001B4 (0x7A55A073) csrrs x0, 0x7a5, x11 reset_vector+352 [86] [M]: 0x00000000800001B8 (0x30551073) csrrw x0, mtvec, x10 reset_vector+356 [87] [M]: 0x00000000800001BC (0x30046073) csrrsi x0, mstatus, 0x8 reset_vector+360 [88] [M]: 0x00000000800001C0 (0x7A001073) csrrw x0, tselect, x0 reset_vector+364 [89] [M]: 0x00000000800001C4 (0x7A0025F3) csrrs x11, tselect, x0 reset_vector+368 [90] [M]: 0x00000000800001C8 (0x10B01663) bne x0, x11, 0x10c reset_vector+372 [91] [M]: 0x00000000800002D4 (0x0FF0000F) fence iorw, iorw pass+0 [92] [M]: 0x00000000800002D8 (0x00100193) addi x3, x0, 0x1 pass+4 [93] [M]: 0x00000000800002DC (0x05D00893) addi x17, x0, 0x5d pass+8 [94] [M]: 0x00000000800002E0 (0x00000513) addi x10, x0, 0x0 pass+12 [95] [M]: 0x00000000800002E4 (0x00000073) ecall pass+16 [96] [M]: 0x0000000080000004 (0x34202F73) csrrs x30, mcause, x0 trap_vector+0 [97] [M]: 0x0000000080000008 (0x00800F93) addi x31, x0, 0x8 trap_vector+4 [98] [M]: 0x000000008000000C (0x03FF0A63) beq x30, x31, 0x34 trap_vector+8 [99] [M]: 0x0000000080000010 (0x00900F93) addi x31, x0, 0x9 trap_vector+12 [100] [M]: 0x0000000080000014 (0x03FF0663) beq x30, x31, 0x2c trap_vector+16 [101] [M]: 0x0000000080000018 (0x00B00F93) addi x31, x0, 0xb trap_vector+20 [102] [M]: 0x000000008000001C (0x03FF0263) beq x30, x31, 0x24 trap_vector+24 [103] [M]: 0x0000000080000040 (0x00001F17) auipc x30, 0x1 write_tohost+0 [104] [M]: 0x0000000080000044 (0xFC3F2023) sw x3, -0x40(x30) write_tohost+4 [105] [M]: 0x0000000080000048 (0x00001F17) auipc x30, 0x1 write_tohost+8 [106] [M]: 0x000000008000004C (0xFA0F2E23) sw x0, -0x44(x30) write_tohost+12 SUCCESS ``` --------- Signed-off-by: Tim Hutt <tdhutt@gmail.com> Co-authored-by: Jordan Carlin <jordanmcarlin@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-15 22:00:39 +0000