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2019-05-02Push address calculation inside the data_check_addr hook and rename it to dat...rmn30Robert Norton3-17/+27
2019-05-01Add base address register as extra argument to ext_data_check_addr hook to as...Robert Norton3-6/+6
2019-04-29Update docs for previous commits.Prashanth Mundkur3-7/+19
2019-04-29Add a post decode hook aimed at implementing CHERI capability mode.Robert Norton4-4/+11
2019-04-29Remove unnecessary option in type of decode and decodeCompressed (never retur...Robert Norton2-36/+18
2019-04-26Pull in missed rvfi fix.Prashanth Mundkur1-2/+2
2019-04-25Fix coq build.Prashanth Mundkur1-19/+19
2019-04-25Add missed test files.Prashanth Mundkur5-0/+258
2019-04-25Merge branch 'master' into master-mergePrashanth Mundkur0-0/+0
2019-04-25riscv_extras.lem: update read/write_mem calls with (dummy) addrsize argumentJon French1-18/+18
2019-04-25riscv_extras.lem: update read/write_mem calls with (dummy) addrsize argumentJon French1-18/+18
2019-04-24Add extended model from cheri-merge.Prashanth Mundkur40-747/+1068
2019-04-18It turns out that the problem I was encountering with ARCH=32 was that I was ...Robert Norton1-3/+2
2019-04-18Fix make code so that ARCH=32,64 actually works as expected (use := for immed...Robert Norton1-7/+8
2019-04-18Parameterise memory read/write primitives by address lengthJon French2-20/+20
2019-04-17Fix a 64-bitism.Prashanth Mundkur1-1/+1
2019-04-12Merge branch 'master' into rmem_interpreterrmem_interpreterJon French17-79/+154
2019-04-12ocaml emulator: add ocaml impls for new standard Sail memory functionsJon French1-0/+12
2019-04-10Update Coq memory interfacesBrian Campbell2-32/+39
2019-04-09Add a script to build rv32/rv64 ocaml and c emulators.Prashanth Mundkur1-0/+8
2019-04-09Fix c.addiw to expand to a non-rvc instruction as per spec.Prashanth Mundkur1-7/+2
2019-04-04Add `sys_enable_writable_misa` and `sys_enable_rvc` to Coq extras fileBrian Campbell1-0/+3
2019-04-03Tweak print_* bindings for LemThomas Bauereiss3-4/+10
2019-04-01Add missed lem definitions for sys misa/rvcflags.Prashanth Mundkur2-0/+16
2019-03-29Add a note about 32-bit OS boots.Prashanth Mundkur1-0/+3
2019-03-29Generalize the previous commit to handle hardwired misa.c.Prashanth Mundkur9-33/+69
2019-03-29Tweak legalize_xepc according to spec: xepc[1] should always be writeable.Robert Norton1-4/+5
2019-03-25Fix prelude for new names of div and mod functions.Robert Norton1-3/+3
2019-03-14Merge branch 'master' into rmem_interpreterJon French594-4948/+102598
2019-03-14Use Bytes.get instead of square bracket notation. I think this is an ocaml ve...Robert Norton1-4/+4
2019-03-13Add workaround for records with len parametersBrian Campbell1-0/+1
2019-03-12Fix missed tlb updates.Prashanth Mundkur2-4/+4
2019-03-12refactor memory access to use new sail intrinsicsJon French3-139/+49
2019-03-12riscv_platform.sail: use externs for platform values even in interpreterJon French3-26/+16
2019-03-12fix missing separator in shift instruction disassembliesJon French1-2/+2
2019-03-12prelude.sail: fix print_foo externs in interpreterJon French1-4/+4
2019-03-12Makefile: generate toFromInterp and marshalled defs for RMEMJon French1-8/+16
2019-03-11Fix rvfi initialization.Prashanth Mundkur1-2/+1
2019-03-11Fix typo in Makefile.Prashanth Mundkur1-1/+1
2019-03-11Add tlbs for Sv32 and Sv48, and some fixes to sfence.vma.Prashanth Mundkur5-50/+171
2019-03-11Fixes for Sv39 TLB.Prashanth Mundkur9-13/+44
2019-03-08Initial attempt at genericizing TLB entries, and re-introduce for Sv39.Prashanth Mundkur2-80/+124
2019-03-08Another prelude cleanup.Prashanth Mundkur1-2/+0
2019-03-07Minor prelude cleanup.Prashanth Mundkur1-2/+0
2019-03-07Get rvfi building again.Prashanth Mundkur3-12/+17
2019-03-07Fix docs about sel4 boot.Prashanth Mundkur3-7/+56
2019-03-07More doc tweaks.Prashanth Mundkur1-3/+5
2019-03-07Another doc update.Prashanth Mundkur1-1/+4
2019-03-07More doc tweaks.Prashanth Mundkur1-20/+13
2019-03-07More doc tweaks.Prashanth Mundkur4-0/+9
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