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-rw-r--r--ocaml_emulator/platform.ml2
-rw-r--r--ocaml_emulator/riscv_ocaml_sim.ml3
2 files changed, 5 insertions, 0 deletions
diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml
index 1e61165..e4dbfeb 100644
--- a/ocaml_emulator/platform.ml
+++ b/ocaml_emulator/platform.ml
@@ -12,6 +12,7 @@ let config_enable_misaligned_access = ref false
let config_mtval_has_illegal_inst_bits = ref false
let config_enable_pmp = ref false
let config_enable_writable_fiom = ref true
+let config_enable_vext = ref true
let platform_arch = ref P.RV64
@@ -79,6 +80,7 @@ let enable_writable_misa () = !config_enable_writable_misa
let enable_rvc () = !config_enable_rvc
let enable_next () = !config_enable_next
let enable_fdext () = false
+let enable_vext () = !config_enable_vext
let enable_dirty_update () = !config_enable_dirty_update
let enable_misaligned_access () = !config_enable_misaligned_access
let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits
diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml
index 814f887b9..c151d69 100644
--- a/ocaml_emulator/riscv_ocaml_sim.ml
+++ b/ocaml_emulator/riscv_ocaml_sim.ml
@@ -56,6 +56,9 @@ let options = Arg.align ([("-dump-dts",
("-disable-rvc",
Arg.Clear P.config_enable_rvc,
" disable the RVC extension on boot");
+ ("-disable-vext",
+ Arg.Clear P.config_enable_vext,
+ " disable the RVV extension on boot");
("-disable-writable-misa-c",
Arg.Clear P.config_enable_writable_misa,
" leave misa hardwired to its initial value");