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Diffstat (limited to 'model/riscv_vext_regs.sail')
| -rw-r--r-- | model/riscv_vext_regs.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_vext_regs.sail b/model/riscv_vext_regs.sail index b74e081..9b81e32 100644 --- a/model/riscv_vext_regs.sail +++ b/model/riscv_vext_regs.sail @@ -202,7 +202,7 @@ function wV (r, in_v) = { let VLEN = unsigned(vlenb) * 8; assert(0 < VLEN & VLEN <= sizeof(vlenmax)); if get_config_print_reg() - then print_reg("v" ^ string_of_int(r) ^ " <- " ^ BitStr(v[VLEN - 1 .. 0])); + then print_reg("v" ^ dec_str(r) ^ " <- " ^ BitStr(v[VLEN - 1 .. 0])); } function rV_bits(i: bits(5)) -> vregtype = rV(unsigned(i)) |