diff options
Diffstat (limited to 'model/riscv_softfloat_interface.sail')
| -rw-r--r-- | model/riscv_softfloat_interface.sail | 119 |
1 files changed, 87 insertions, 32 deletions
diff --git a/model/riscv_softfloat_interface.sail b/model/riscv_softfloat_interface.sail index 8c017dd..0a055cb 100644 --- a/model/riscv_softfloat_interface.sail +++ b/model/riscv_softfloat_interface.sail @@ -28,50 +28,105 @@ type bits_WU = bits(32) /* Unsigned integer */ type bits_L = bits(64) /* Signed integer */ type bits_LU = bits(64) /* Unsigned integer */ +/* ***************************************************************** */ +/* Internal registers to pass results across the softfloat interface + * to avoid return types involving structures. + */ +register float_result : bits(64) +register float_fflags : bits(64) + /* **************************************************************** */ /* ADD/SUB/MUL/DIV */ -val riscv_f32Add : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) -function riscv_f32Add (rm, v1, v2) = (0b_00000, 0x_0000_0000) - -val riscv_f32Sub : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) -function riscv_f32Sub (rm, v1, v2) = (0b_00000, 0x_0000_0000) - -val riscv_f32Mul : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) -function riscv_f32Mul (rm, v1, v2) = (0b_00000, 0x_0000_0000) - -val riscv_f32Div : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) -function riscv_f32Div (rm, v1, v2) = (0b_00000, 0x_0000_0000) - -val riscv_f64Add : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) -function riscv_f64Add (rm, v1, v2) = (0b_00000, 0x_0000_0000_0000_0000) - -val riscv_f64Sub : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) -function riscv_f64Sub (rm, v1, v2) = (0b_00000, 0x_0000_0000_0000_0000) - -val riscv_f64Mul : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) -function riscv_f64Mul (rm, v1, v2) = (0b_00000, 0x_0000_0000_0000_0000) - -val riscv_f64Div : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) -function riscv_f64Div (rm, v1, v2) = (0b_00000, 0x_0000_0000_0000_0000) +val extern_f32Add = {c: "softfloat_f32add"} : (bits_rm, bits_S, bits_S) -> unit +val riscv_f32Add : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Add (rm, v1, v2) = { + extern_f32Add(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} + +val extern_f32Sub = {c: "softfloat_f32sub"} : (bits_rm, bits_S, bits_S) -> unit +val riscv_f32Sub : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Sub (rm, v1, v2) = { + extern_f32Sub(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} + +val extern_f32Mul = {c: "softfloat_f32mul"} : (bits_rm, bits_S, bits_S) -> unit +val riscv_f32Mul : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Mul (rm, v1, v2) = { + extern_f32Mul(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} + +val extern_f32Div = {c: "softfloat_f32div"} : (bits_rm, bits_S, bits_S) -> unit +val riscv_f32Div : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Div (rm, v1, v2) = { + extern_f32Div(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} + +val extern_f64Add = {c: "softfloat_f64add"} : (bits_rm, bits_D, bits_D) -> unit +val riscv_f64Add : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Add (rm, v1, v2) = { + extern_f64Add(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} + +val extern_f64Sub = {c: "softfloat_f64sub"} : (bits_rm, bits_D, bits_D) -> unit +val riscv_f64Sub : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Sub (rm, v1, v2) = { + extern_f64Sub(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} + +val extern_f64Mul = {c: "softfloat_f64mul"} : (bits_rm, bits_D, bits_D) -> unit +val riscv_f64Mul : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Mul (rm, v1, v2) = { + extern_f64Mul(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} + +val extern_f64Div = {c: "softfloat_f64div"} : (bits_rm, bits_D, bits_D) -> unit +val riscv_f64Div : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Div (rm, v1, v2) = { + extern_f64Div(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} /* **************************************************************** */ /* MULTIPLY-ADD */ -val riscv_f32MulAdd : (bits_rm, bits_S, bits_S, bits_S) -> (bits_fflags, bits_S) -function riscv_f32MulAdd (rm, v1, v2, v3) = (0b_00000, 0x_0000_0000) +val extern_f32MulAdd = {c: "softfloat_f32muladd"} : (bits_rm, bits_S, bits_S, bits_S) -> unit +val riscv_f32MulAdd : (bits_rm, bits_S, bits_S, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32MulAdd (rm, v1, v2, v3) = { + extern_f32MulAdd(rm, v1, v2, v3); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} -val riscv_f64MulAdd : (bits_rm, bits_D, bits_D, bits_D) -> (bits_fflags, bits_D) -function riscv_f64MulAdd (rm, v1, v2, v3) = (0b_00000, 0x_0000_0000_0000_0000) +val extern_f64MulAdd = {c: "softfloat_f64muladd"} : (bits_rm, bits_D, bits_D, bits_D) -> unit +val riscv_f64MulAdd : (bits_rm, bits_D, bits_D, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64MulAdd (rm, v1, v2, v3) = { + extern_f64MulAdd(rm, v1, v2, v3); + (float_fflags[4 .. 0], float_result) +} /* **************************************************************** */ /* SQUARE ROOT */ -val riscv_f32Sqrt : (bits_rm, bits_S) -> (bits_fflags, bits_S) -function riscv_f32Sqrt (rm, v) = (0b_00000, 0x_0000_0000) - -val riscv_f64Sqrt : (bits_rm, bits_D) -> (bits_fflags, bits_D) -function riscv_f64Sqrt (rm, v) = (0b_00000, 0x_0000_0000_0000_0000) +val extern_f32Sqrt = {c: "softfloat_f32sqrt"} : (bits_rm, bits_S) -> unit +val riscv_f32Sqrt : (bits_rm, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Sqrt (rm, v) = { + extern_f32Sqrt(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} + +val extern_f64Sqrt = {c: "softfloat_f64sqrt"} : (bits_rm, bits_D) -> unit +val riscv_f64Sqrt : (bits_rm, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Sqrt (rm, v) = { + extern_f64Sqrt(rm, v); + (float_fflags[4 .. 0], float_result) +} /* **************************************************************** */ /* CONVERSIONS */ |