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-rw-r--r--model/riscv_regs.sail4
1 files changed, 3 insertions, 1 deletions
diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail
index 09f22ff..36f8236 100644
--- a/model/riscv_regs.sail
+++ b/model/riscv_regs.sail
@@ -143,7 +143,7 @@ overload X = {rX, wX}
/* register names */
-val cast reg_name_abi : regidx -> string
+val reg_name_abi : regidx -> string
function reg_name_abi(r) = {
match (r) {
@@ -182,6 +182,8 @@ function reg_name_abi(r) = {
}
}
+overload to_str = {reg_name_abi}
+
/* mappings for assembly */
val reg_name : bits(5) <-> string