diff options
Diffstat (limited to 'model/riscv_regs.sail')
-rw-r--r-- | model/riscv_regs.sail | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail index 64002fa..b75c029 100644 --- a/model/riscv_regs.sail +++ b/model/riscv_regs.sail @@ -154,49 +154,6 @@ function wX_bits(i: bits(5), data: xlenbits) -> unit = { overload X = {rX_bits, wX_bits, rX, wX} -/* register names */ - -val reg_name_abi : regidx -> string - -function reg_name_abi(r) = { - match (r) { - 0b00000 => "zero", - 0b00001 => "ra", - 0b00010 => "sp", - 0b00011 => "gp", - 0b00100 => "tp", - 0b00101 => "t0", - 0b00110 => "t1", - 0b00111 => "t2", - 0b01000 => "fp", - 0b01001 => "s1", - 0b01010 => "a0", - 0b01011 => "a1", - 0b01100 => "a2", - 0b01101 => "a3", - 0b01110 => "a4", - 0b01111 => "a5", - 0b10000 => "a6", - 0b10001 => "a7", - 0b10010 => "s2", - 0b10011 => "s3", - 0b10100 => "s4", - 0b10101 => "s5", - 0b10110 => "s6", - 0b10111 => "s7", - 0b11000 => "s8", - 0b11001 => "s9", - 0b11010 => "s10", - 0b11011 => "s11", - 0b11100 => "t3", - 0b11101 => "t4", - 0b11110 => "t5", - 0b11111 => "t6" - } -} - -overload to_str = {reg_name_abi} - /* mappings for assembly */ val reg_name : bits(5) <-> string |