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-rw-r--r--model/riscv_jalr_seq.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail
index 0f4abd0..ea41ce4 100644
--- a/model/riscv_jalr_seq.sail
+++ b/model/riscv_jalr_seq.sail
@@ -24,7 +24,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
},
Ext_ControlAddr_OK(addr) => {
let target = [addr with 0 = bitzero]; /* clear addr[0] */
- if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C)) then {
+ if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca)) then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
} else {