diff options
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 18 |
1 files changed, 16 insertions, 2 deletions
@@ -18,6 +18,16 @@ else $(error '$(ARCH)' is not a valid architecture, must be one of: RV32, RV64) endif +# Platforms currently only select HPM events. +HPM_PLATFORM ?= DEFAULT +ifeq ($(HPM_PLATFORM), EXAMPLE) + EVENT_ENUMS := platform/example_event_def.enums + EVENT_IMPL := platform/riscv_events_example.c +else +# no event enum file + EVENT_IMPL := riscv_platform_events.c +endif + # Instruction sources, depending on target SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail @@ -108,8 +118,8 @@ export LEM_DIR C_WARNINGS ?= #-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function -C_INCS = $(addprefix c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h riscv_hpmevents.h riscv_hpmevents_impl.h riscv_softfloat.h) -C_SRCS = $(addprefix c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_hpmevents.c riscv_platform_events.c riscv_softfloat.c riscv_sim.c) +C_INCS = $(addprefix c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h riscv_hpmevents.h riscv_hpmevents_impl.h riscv_softfloat.h $(EVENT_ENUMS)) +C_SRCS = $(addprefix c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_hpmevents.c $(EVENT_IMPL) riscv_softfloat.c riscv_sim.c) # portability for MacPorts/MacOS C_SYS_INCLUDES = -I /opt/local/include @@ -125,6 +135,10 @@ SOFTFLOAT_SPECIALIZE_TYPE = RISCV C_FLAGS = -DARCH=$(ARCH) $(C_SYS_INCLUDES) -I $(SAIL_LIB_DIR) -I c_emulator $(SOFTFLOAT_FLAGS) -fcommon C_LIBS = $(C_SYS_LIBDIRS) -lgmp -lz $(SOFTFLOAT_LIBS) +ifneq (,$(EVENT_ENUMS)) +C_FLAGS += -DEVENT_ENUMS=\"$(EVENT_ENUMS)\" +endif + # The C simulator can be built to be linked against Spike for tandem-verification. # This needs the C bindings to Spike from https://github.com/SRI-CSL/l3riscv # TV_SPIKE_DIR in the environment should point to the top-level dir of the L3 |