diff options
| -rw-r--r-- | c_emulator/riscv_sim.c | 22 | ||||
| -rw-r--r-- | model/riscv_sys_control.sail | 6 | ||||
| -rw-r--r-- | model/riscv_sys_exceptions.sail | 12 |
3 files changed, 30 insertions, 10 deletions
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index c70b31c..69f7423 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -79,7 +79,6 @@ static struct option options[] = { {"disable-compressed", no_argument, 0, 'C'}, {"disable-writable-misa", no_argument, 0, 'I'}, {"mtval-has-illegal-inst-bits", no_argument, 0, 'i'}, - {"dump-dts", no_argument, 0, 's'}, {"device-tree-blob", required_argument, 0, 'b'}, {"terminal-log", required_argument, 0, 't'}, {"show-times", required_argument, 0, 'p'}, @@ -172,7 +171,7 @@ char *process_args(int argc, char **argv) int c, idx = 1; uint64_t ram_size = 0; while(true) { - c = getopt_long(argc, argv, "admCspz:b:t:v:hr:T:", options, &idx); + c = getopt_long(argc, argv, "admCIispz:b:t:v:hr:T:", options, &idx); if (c == -1) break; switch (c) { case 'a': @@ -187,18 +186,22 @@ char *process_args(int argc, char **argv) rv_enable_misaligned = true; break; case 'C': + fprintf(stderr, "enabling RVC compressed instructions.\n"); rv_enable_rvc = false; break; case 'I': + fprintf(stderr, "enabling writable misa CSR.\n"); rv_enable_writable_misa = false; break; case 'i': + fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n"); rv_mtval_has_illegal_inst_bits = true; break; case 's': do_dump_dts = true; break; case 'p': + fprintf(stderr, "will show execution times on completion.\n"); do_show_times = true; break; case 'z': @@ -206,16 +209,22 @@ char *process_args(int argc, char **argv) if (ram_size) { fprintf(stderr, "setting ram-size to %" PRIu64 " MB\n", ram_size); rv_ram_size = ram_size << 20; + } else { + fprintf(stderr, "invalid ram-size '%s' provided.\n", optarg); + exit(1); } break; case 'b': dtb_file = strdup(optarg); + fprintf(stderr, "using %s as DTB file.\n", dtb_file); break; case 't': term_log = strdup(optarg); + fprintf(stderr, "using %s for terminal output.\n", term_log); break; case 'T': sig_file = strdup(optarg); + fprintf(stderr, "using %s for test-signature output.\n", term_log); break; case 'h': print_usage(argv[0], 0); @@ -224,18 +233,19 @@ char *process_args(int argc, char **argv) case 'r': rvfi_dii = true; rvfi_dii_port = atoi(optarg); + fprintf(stderr, "using %d as RVFI port.\n", rvfi_dii_port); break; #endif - default: - fprintf(stderr, "Unrecognized optchar %c\n", c); - print_usage(argv[0], 1); } } if (do_dump_dts) dump_dts(); #ifdef RVFI_DII if (idx > argc || (idx == argc && !rvfi_dii)) print_usage(argv[0], 0); #else - if (optind >= argc) print_usage(argv[0], 0); + if (optind >= argc) { + fprintf(stderr, "No elf file provided.\n"); + print_usage(argv[0], 0); + } #endif if (term_log == NULL) term_log = strdup("term.log"); if (dtb_file) read_dtb(dtb_file); diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 6bee610..e866986 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -366,7 +366,7 @@ function exception_handler(cur_priv : Privilege, ctl : ctl_result, print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); cancel_reservation(); - get_xret_target(Machine) & pc_alignment_mask() + prepare_xret_target(Machine) & pc_alignment_mask() }, (_, CTL_SRET()) => { let prev_priv = cur_privilege; @@ -380,7 +380,7 @@ function exception_handler(cur_priv : Privilege, ctl : ctl_result, print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); cancel_reservation(); - get_xret_target(Supervisor) & pc_alignment_mask() + prepare_xret_target(Supervisor) & pc_alignment_mask() }, (_, CTL_URET()) => { let prev_priv = cur_privilege; @@ -392,7 +392,7 @@ function exception_handler(cur_priv : Privilege, ctl : ctl_result, print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); cancel_reservation(); - get_xret_target(User) & pc_alignment_mask() + prepare_xret_target(User) & pc_alignment_mask() } } } diff --git a/model/riscv_sys_exceptions.sail b/model/riscv_sys_exceptions.sail index d2be25f..94d869e 100644 --- a/model/riscv_sys_exceptions.sail +++ b/model/riscv_sys_exceptions.sail @@ -17,7 +17,13 @@ function prepare_trap_vector(p : Privilege, cause : Mcause) -> xlenbits = { } } -/* used for xRET */ +/* xRET handling involves three functions: + * + * get_xret_target: used to read the value of the xret target (no control flow transfer) + * set_xret_target: used to write a value of the xret target (no control flow transfer) + * prepare_xret_target: used to get the value for control transfer to the xret target + */ + val get_xret_target : Privilege -> xlenbits effect {rreg} function get_xret_target(p) = match p { @@ -37,6 +43,10 @@ function set_xret_target(p, value) = { target } +val prepare_xret_target : (Privilege) -> xlenbits effect {rreg, wreg} +function prepare_xret_target(p) = + get_xret_target(p) + /* other trap-related CSRs */ function get_mtvec() -> xlenbits = |