diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | model/riscv_csr_ext.sail | 20 | ||||
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 4 | ||||
| -rw-r--r-- | model/riscv_next_control.sail | 6 | ||||
| -rw-r--r-- | model/riscv_sys_control.sail | 4 |
5 files changed, 28 insertions, 7 deletions
@@ -30,6 +30,7 @@ SAIL_SYS_SRCS += riscv_next_regs.sail SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model SAIL_SYS_SRCS += riscv_next_control.sail # helpers for the 'N' extension +SAIL_SYS_SRCS += riscv_csr_ext.sail # access to CSR extensions SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail diff --git a/model/riscv_csr_ext.sail b/model/riscv_csr_ext.sail new file mode 100644 index 0000000..ea4f065 --- /dev/null +++ b/model/riscv_csr_ext.sail @@ -0,0 +1,20 @@ +/* Extensions may want to add additional CSR registers to the CSR address map. + * These functions support access to such registers. + * + * The default implementation provides access to the CSRs added by the 'N' + * extension. + */ + +/* returns whether a CSR is defined and accessible at a given address + * and privilege + */ +function ext_is_CSR_defined(csr : csreg, p : Privilege) -> bool = + is_NExt_CSR_defined(csr, p) // 'N' extension + +/* returns the value of the CSR if it is defined */ +function ext_read_CSR(csr : csreg) -> option(xlenbits) = + read_NExt_CSR(csr) + +/* returns false if the CSR is not defined or if the write is unsuccessful */ +function ext_write_CSR(csr : csreg, value : xlenbits) -> bool = + write_NExt_CSR(csr, value) diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index ccbc030..9a2cf9f 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -69,7 +69,7 @@ function readCSR csr : csreg -> xlenbits = { (0xC82, 32) => minstret[63 .. 32], _ => /* check extensions */ - match read_UExt_CSR(csr) { + match ext_read_CSR(csr) { Some(res) => res, None() => { print_bits("unhandled read to CSR ", csr); EXTZ(0x0) } @@ -127,7 +127,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { match res { Some(v) => print_reg("CSR " ^ csr ^ " <- " ^ BitStr(v) ^ " (input: " ^ BitStr(value) ^ ")"), None() => { /* check extensions */ - if write_UExt_CSR(csr, value) + if ext_write_CSR(csr, value) then () else print_bits("unhandled write to CSR ", csr) } diff --git a/model/riscv_next_control.sail b/model/riscv_next_control.sail index 009bccc..6034aae 100644 --- a/model/riscv_next_control.sail +++ b/model/riscv_next_control.sail @@ -1,6 +1,6 @@ /* Functional specification for the 'N' user-level interrupts standard extension. */ -function is_UExt_CSR_defined(csr : bits(12), p : Privilege) -> bool = +function is_NExt_CSR_defined(csr : bits(12), p : Privilege) -> bool = match (csr) { 0x000 => haveUsrMode(), // ustatus 0x004 => haveUsrMode(), // uie @@ -13,7 +13,7 @@ function is_UExt_CSR_defined(csr : bits(12), p : Privilege) -> bool = _ => false } -function read_UExt_CSR csr : csreg -> option(xlenbits) = { +function read_NExt_CSR csr : csreg -> option(xlenbits) = { let res : option(xlenbits) = match csr { 0x000 => Some(lower_sstatus(lower_mstatus(mstatus)).bits()), @@ -29,7 +29,7 @@ function read_UExt_CSR csr : csreg -> option(xlenbits) = { res } -function write_UExt_CSR(csr : csreg, value : xlenbits) -> bool = { +function write_NExt_CSR(csr : csreg, value : xlenbits) -> bool = { let res : option(xlenbits) = match csr { 0x000 => { mstatus = legalize_ustatus(mstatus, value); Some(mstatus.bits()) }, diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 52111f1..6bee610 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -6,7 +6,7 @@ function csrAccess(csr : csreg) -> csrRW = csr[11..10] function csrPriv(csr : csreg) -> priv_level = csr[9..8] -function is_CSR_defined (csr : bits(12), p : Privilege) -> bool = +function is_CSR_defined (csr : csreg, p : Privilege) -> bool = match (csr) { /* machine mode: informational */ 0xf11 => p == Machine, // mvendorid @@ -69,7 +69,7 @@ function is_CSR_defined (csr : bits(12), p : Privilege) -> bool = 0xC82 => p == User & (sizeof(xlen) == 32), // instreth /* check extensions */ - _ => is_UExt_CSR_defined(csr, p) // 'N' extension + _ => ext_is_CSR_defined(csr, p) } val check_CSR_access : (csrRW, priv_level, Privilege, bool) -> bool |