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-rw-r--r--Makefile6
-rw-r--r--model/riscv_fetch.sail2
-rw-r--r--model/riscv_fetch_rvfi.sail2
-rw-r--r--model/riscv_insts_base.sail7
-rw-r--r--model/riscv_insts_zca.sail (renamed from model/riscv_insts_cext.sail)143
-rw-r--r--model/riscv_insts_zcd.sail (renamed from model/riscv_insts_cdext.sail)33
-rw-r--r--model/riscv_insts_zcf.sail (renamed from model/riscv_insts_cfext.sail)28
-rw-r--r--model/riscv_jalr_seq.sail2
-rw-r--r--model/riscv_step.sail2
9 files changed, 105 insertions, 120 deletions
diff --git a/Makefile b/Makefile
index 268e36b..e26ee29 100644
--- a/Makefile
+++ b/Makefile
@@ -23,9 +23,9 @@ SAIL_VLEN := riscv_vlen.sail
# Instruction sources, depending on target
SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
-SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
-SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail
-SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail
+SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
+SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
+SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail
SAIL_DEFAULT_INST += riscv_insts_svinval.sail
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail
index 78401c8..480f47e 100644
--- a/model/riscv_fetch.sail
+++ b/model/riscv_fetch.sail
@@ -19,7 +19,7 @@ function fetch() -> FetchResult =
match ext_fetch_check_pc(PC, PC) {
Ext_FetchAddr_Error(e) => F_Ext_Error(e),
Ext_FetchAddr_OK(use_pc) => {
- if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_C))))
+ if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
then F_Error(E_Fetch_Addr_Align(), PC)
else match translateAddr(use_pc, Execute()) {
TR_Failure(e, _) => F_Error(e, PC),
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail
index 3f66232..ab09d26 100644
--- a/model/riscv_fetch_rvfi.sail
+++ b/model/riscv_fetch_rvfi.sail
@@ -17,7 +17,7 @@ function fetch() -> FetchResult = {
Ext_FetchAddr_Error(e) => F_Ext_Error(e),
Ext_FetchAddr_OK(use_pc) => {
/* then check PC alignment */
- if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_C))))
+ if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
then F_Error(E_Fetch_Addr_Align(), PC)
else match translateAddr(use_pc, Execute()) {
TR_Failure(e, _) => F_Error(e, PC),
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
index 599c0a7..438fa15 100644
--- a/model/riscv_insts_base.sail
+++ b/model/riscv_insts_base.sail
@@ -12,6 +12,9 @@
enum clause extension = Ext_C
function clause extensionEnabled(Ext_C) = misa[C] == 0b1
+enum clause extension = Ext_Zca
+function clause extensionEnabled(Ext_Zca) = extensionEnabled(Ext_C)
+
/* ****************************************************************** */
union clause ast = UTYPE : (bits(20), regidx, uop)
@@ -69,7 +72,7 @@ function clause execute (RISCV_JAL(imm, rd)) = {
},
Ext_ControlAddr_OK(target) => {
/* Perform standard alignment check */
- if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C))
+ if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca))
then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
@@ -133,7 +136,7 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = {
RETIRE_FAIL
},
Ext_ControlAddr_OK(target) => {
- if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C)) then {
+ if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca)) then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL;
} else {
diff --git a/model/riscv_insts_cext.sail b/model/riscv_insts_zca.sail
index c93332a..5cc4f26 100644
--- a/model/riscv_insts_cext.sail
+++ b/model/riscv_insts_zca.sail
@@ -7,18 +7,17 @@
/*=======================================================================================*/
/* ********************************************************************* */
-/* This file specifies the compressed instructions in the 'C' extension. */
+/* This file specifies the compressed instructions in the 'Zca' extension. */
-/* These instructions are only legal if misa[C] is true. Instead of
- * checking this in every execute clause, we currently do the check in one place
- * in the fetch-execute logic.
+/* Instead of checking for Zca in every execute clause, we currently do
+ * the check in one place in the fetch-execute logic.
*/
/* ****************************************************************** */
union clause ast = C_NOP : unit
-mapping clause encdec_compressed = C_NOP() if extensionEnabled(Ext_C)
- <-> 0b000 @ 0b0 @ 0b00000 @ 0b00000 @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_NOP() if extensionEnabled(Ext_Zca)
+ <-> 0b000 @ 0b0 @ 0b00000 @ 0b00000 @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute C_NOP() = RETIRE_SUCCESS
@@ -29,9 +28,9 @@ mapping clause assembly = C_NOP() <-> "c.nop"
union clause ast = C_ADDI4SPN : (cregidx, bits(8))
mapping clause encdec_compressed = C_ADDI4SPN(rd, nz96 @ nz54 @ nz3 @ nz2)
- if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000 & extensionEnabled(Ext_C)
+ if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000 & extensionEnabled(Ext_Zca)
<-> 0b000 @ nz54 : bits(2) @ nz96 : bits(4) @ nz2 : bits(1) @ nz3 : bits(1) @ rd : cregidx @ 0b00
- if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000 & extensionEnabled(Ext_C)
+ if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000 & extensionEnabled(Ext_Zca)
function clause execute (C_ADDI4SPN(rdc, nzimm)) = {
let imm : bits(12) = (0b00 @ nzimm @ 0b00);
@@ -47,8 +46,8 @@ mapping clause assembly = C_ADDI4SPN(rdc, nzimm)
/* ****************************************************************** */
union clause ast = C_LW : (bits(5), cregidx, cregidx)
-mapping clause encdec_compressed = C_LW(ui6 @ ui53 @ ui2, rs1, rd) if extensionEnabled(Ext_C)
- <-> 0b010 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_LW(ui6 @ ui53 @ ui2, rs1, rd) if extensionEnabled(Ext_Zca)
+ <-> 0b010 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_Zca)
function clause execute (C_LW(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
@@ -64,9 +63,9 @@ mapping clause assembly = C_LW(uimm, rsc, rdc)
union clause ast = C_LD : (bits(5), cregidx, cregidx)
mapping clause encdec_compressed = C_LD(ui76 @ ui53, rs1, rd)
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_LD(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -83,8 +82,8 @@ mapping clause assembly = C_LD(uimm, rsc, rdc)
/* ****************************************************************** */
union clause ast = C_SW : (bits(5), cregidx, cregidx)
-mapping clause encdec_compressed = C_SW(ui6 @ ui53 @ ui2, rs1, rs2) if extensionEnabled(Ext_C)
- <-> 0b110 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_SW(ui6 @ ui53 @ ui2, rs1, rs2) if extensionEnabled(Ext_Zca)
+ <-> 0b110 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00 if extensionEnabled(Ext_Zca)
function clause execute (C_SW(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
@@ -100,9 +99,9 @@ mapping clause assembly = C_SW(uimm, rsc1, rsc2)
union clause ast = C_SD : (bits(5), cregidx, cregidx)
mapping clause encdec_compressed = C_SD(ui76 @ ui53, rs1, rs2)
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b111 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_SD(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -120,9 +119,9 @@ mapping clause assembly = C_SD(uimm, rsc1, rsc2)
union clause ast = C_ADDI : (bits(6), regidx)
mapping clause encdec_compressed = C_ADDI(nzi5 @ nzi40, rsd)
- if nzi5 @ nzi40 != 0b000000 & rsd != zreg & extensionEnabled(Ext_C)
+ if nzi5 @ nzi40 != 0b000000 & rsd != zreg & extensionEnabled(Ext_Zca)
<-> 0b000 @ nzi5 : bits(1) @ rsd : regidx @ nzi40 : bits(5) @ 0b01
- if nzi5 @ nzi40 != 0b000000 & rsd != zreg & extensionEnabled(Ext_C)
+ if nzi5 @ nzi40 != 0b000000 & rsd != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_ADDI(nzi, rsd)) = {
let imm : bits(12) = sign_extend(nzi);
@@ -138,9 +137,9 @@ mapping clause assembly = C_ADDI(nzi, rsd)
union clause ast = C_JAL : (bits(11))
mapping clause encdec_compressed = C_JAL(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31)
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 32 & extensionEnabled(Ext_Zca)
<-> 0b001 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 32 & extensionEnabled(Ext_Zca)
function clause execute (C_JAL(imm)) =
execute(RISCV_JAL(sign_extend(imm @ 0b0), ra))
@@ -154,9 +153,9 @@ mapping clause assembly = C_JAL(imm)
union clause ast = C_ADDIW : (bits(6), regidx)
mapping clause encdec_compressed = C_ADDIW(imm5 @ imm40, rsd)
- if rsd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if rsd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b001 @ imm5 : bits(1) @ rsd : regidx @ imm40 : bits(5) @ 0b01
- if rsd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if rsd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_ADDIW(imm, rsd)) =
execute(ADDIW(sign_extend(imm), rsd, rsd))
@@ -170,9 +169,9 @@ mapping clause assembly = C_ADDIW(imm, rsd)
union clause ast = C_LI : (bits(6), regidx)
mapping clause encdec_compressed = C_LI(imm5 @ imm40, rd)
- if rd != zreg & extensionEnabled(Ext_C)
+ if rd != zreg & extensionEnabled(Ext_Zca)
<-> 0b010 @ imm5 : bits(1) @ rd : regidx @ imm40 : bits(5) @ 0b01
- if rd != zreg & extensionEnabled(Ext_C)
+ if rd != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_LI(imm, rd)) = {
let imm : bits(12) = sign_extend(imm);
@@ -188,9 +187,9 @@ mapping clause assembly = C_LI(imm, rd)
union clause ast = C_ADDI16SP : (bits(6))
mapping clause encdec_compressed = C_ADDI16SP(nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4)
- if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000 & extensionEnabled(Ext_C)
+ if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000 & extensionEnabled(Ext_Zca)
<-> 0b011 @ nzi9 : bits(1) @ /* x2 */ 0b00010 @ nzi4 : bits(1) @ nzi6 : bits(1) @ nzi87 : bits(2) @ nzi5 : bits(1) @ 0b01
- if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000 & extensionEnabled(Ext_C)
+ if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000 & extensionEnabled(Ext_Zca)
function clause execute (C_ADDI16SP(imm)) = {
let imm : bits(12) = sign_extend(imm @ 0x0);
@@ -206,9 +205,9 @@ mapping clause assembly = C_ADDI16SP(imm)
union clause ast = C_LUI : (bits(6), regidx)
mapping clause encdec_compressed = C_LUI(imm17 @ imm1612, rd)
- if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 & extensionEnabled(Ext_C)
+ if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 & extensionEnabled(Ext_Zca)
<-> 0b011 @ imm17 : bits(1) @ rd : regidx @ imm1612 : bits(5) @ 0b01
- if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 & extensionEnabled(Ext_C)
+ if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 & extensionEnabled(Ext_Zca)
function clause execute (C_LUI(imm, rd)) = {
let res : bits(20) = sign_extend(imm);
@@ -224,9 +223,9 @@ mapping clause assembly = C_LUI(imm, rd)
union clause ast = C_SRLI : (bits(6), cregidx)
mapping clause encdec_compressed = C_SRLI(nzui5 @ nzui40, rsd)
- if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_C)
+ if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_Zca)
<-> 0b100 @ nzui5 : bits(1) @ 0b00 @ rsd : cregidx @ nzui40 : bits(5) @ 0b01
- if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_C)
+ if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_Zca)
function clause execute (C_SRLI(shamt, rsd)) = {
let rsd = creg2reg_idx(rsd);
@@ -242,9 +241,9 @@ mapping clause assembly = C_SRLI(shamt, rsd)
union clause ast = C_SRAI : (bits(6), cregidx)
mapping clause encdec_compressed = C_SRAI(nzui5 @ nzui40, rsd)
- if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_C)
+ if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_Zca)
<-> 0b100 @ nzui5 : bits(1) @ 0b01 @ rsd : cregidx @ nzui40 : bits(5) @ 0b01
- if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_C)
+ if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_Zca)
function clause execute (C_SRAI(shamt, rsd)) = {
let rsd = creg2reg_idx(rsd);
@@ -259,8 +258,8 @@ mapping clause assembly = C_SRAI(shamt, rsd)
/* ****************************************************************** */
union clause ast = C_ANDI : (bits(6), cregidx)
-mapping clause encdec_compressed = C_ANDI(i5 @ i40, rsd) if extensionEnabled(Ext_C)
- <-> 0b100 @ i5 : bits(1) @ 0b10 @ rsd : cregidx @ i40 : bits(5) @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_ANDI(i5 @ i40, rsd) if extensionEnabled(Ext_Zca)
+ <-> 0b100 @ i5 : bits(1) @ 0b10 @ rsd : cregidx @ i40 : bits(5) @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_ANDI(imm, rsd)) = {
let rsd = creg2reg_idx(rsd);
@@ -273,8 +272,8 @@ mapping clause assembly = C_ANDI(imm, rsd)
/* ****************************************************************** */
union clause ast = C_SUB : (cregidx, cregidx)
-mapping clause encdec_compressed = C_SUB(rsd, rs2) if extensionEnabled(Ext_C)
- <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b00 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_SUB(rsd, rs2) if extensionEnabled(Ext_Zca)
+ <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b00 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_SUB(rsd, rs2)) = {
let rsd = creg2reg_idx(rsd);
@@ -288,8 +287,8 @@ mapping clause assembly = C_SUB(rsd, rs2)
/* ****************************************************************** */
union clause ast = C_XOR : (cregidx, cregidx)
-mapping clause encdec_compressed = C_XOR(rsd, rs2) if extensionEnabled(Ext_C)
- <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b01 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_XOR(rsd, rs2) if extensionEnabled(Ext_Zca)
+ <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b01 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_XOR(rsd, rs2)) = {
let rsd = creg2reg_idx(rsd);
@@ -303,8 +302,8 @@ mapping clause assembly = C_XOR(rsd, rs2)
/* ****************************************************************** */
union clause ast = C_OR : (cregidx, cregidx)
-mapping clause encdec_compressed = C_OR(rsd, rs2) if extensionEnabled(Ext_C)
- <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b10 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_OR(rsd, rs2) if extensionEnabled(Ext_Zca)
+ <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b10 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_OR(rsd, rs2)) = {
let rsd = creg2reg_idx(rsd);
@@ -318,8 +317,8 @@ mapping clause assembly = C_OR(rsd, rs2)
/* ****************************************************************** */
union clause ast = C_AND : (cregidx, cregidx)
-mapping clause encdec_compressed = C_AND(rsd, rs2) if extensionEnabled(Ext_C)
- <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b11 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_AND(rsd, rs2) if extensionEnabled(Ext_Zca)
+ <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b11 @ rs2 : cregidx @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_AND(rsd, rs2)) = {
let rsd = creg2reg_idx(rsd);
@@ -334,9 +333,9 @@ mapping clause assembly = C_AND(rsd, rs2)
union clause ast = C_SUBW : (cregidx, cregidx)
mapping clause encdec_compressed = C_SUBW(rsd, rs2)
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b100 @ 0b1 @ 0b11 @ rsd : cregidx @ 0b00 @ rs2 : cregidx @ 0b01
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_SUBW(rsd, rs2)) = {
let rsd = creg2reg_idx(rsd);
@@ -353,9 +352,9 @@ mapping clause assembly = C_SUBW(rsd, rs2)
union clause ast = C_ADDW : (cregidx, cregidx)
mapping clause encdec_compressed = C_ADDW(rsd, rs2)
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b100 @ 0b1 @ 0b11 @ rsd : cregidx @ 0b01 @ rs2 : cregidx @ 0b01
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_ADDW(rsd, rs2)) = {
let rsd = creg2reg_idx(rsd);
@@ -371,8 +370,8 @@ mapping clause assembly = C_ADDW(rsd, rs2)
/* ****************************************************************** */
union clause ast = C_J : (bits(11))
-mapping clause encdec_compressed = C_J(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31) if extensionEnabled(Ext_C)
- <-> 0b101 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_J(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31) if extensionEnabled(Ext_Zca)
+ <-> 0b101 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_J(imm)) =
execute(RISCV_JAL(sign_extend(imm @ 0b0), zreg))
@@ -383,8 +382,8 @@ mapping clause assembly = C_J(imm)
/* ****************************************************************** */
union clause ast = C_BEQZ : (bits(8), cregidx)
-mapping clause encdec_compressed = C_BEQZ(i8 @ i76 @ i5 @ i43 @ i21, rs) if extensionEnabled(Ext_C)
- <-> 0b110 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregidx @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_BEQZ(i8 @ i76 @ i5 @ i43 @ i21, rs) if extensionEnabled(Ext_Zca)
+ <-> 0b110 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregidx @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_BEQZ(imm, rs)) =
execute(BTYPE(sign_extend(imm @ 0b0), zreg, creg2reg_idx(rs), RISCV_BEQ))
@@ -395,8 +394,8 @@ mapping clause assembly = C_BEQZ(imm, rs)
/* ****************************************************************** */
union clause ast = C_BNEZ : (bits(8), cregidx)
-mapping clause encdec_compressed = C_BNEZ(i8 @ i76 @ i5 @ i43 @ i21, rs) if extensionEnabled(Ext_C)
- <-> 0b111 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregidx @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_BNEZ(i8 @ i76 @ i5 @ i43 @ i21, rs) if extensionEnabled(Ext_Zca)
+ <-> 0b111 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregidx @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01 if extensionEnabled(Ext_Zca)
function clause execute (C_BNEZ(imm, rs)) =
execute(BTYPE(sign_extend(imm @ 0b0), zreg, creg2reg_idx(rs), RISCV_BNE))
@@ -408,9 +407,9 @@ mapping clause assembly = C_BNEZ(imm, rs)
union clause ast = C_SLLI : (bits(6), regidx)
mapping clause encdec_compressed = C_SLLI(nzui5 @ nzui40, rsd)
- if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_C)
+ if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_Zca)
<-> 0b000 @ nzui5 : bits(1) @ rsd : regidx @ nzui40 : bits(5) @ 0b10
- if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_C)
+ if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0) & extensionEnabled(Ext_Zca)
function clause execute (C_SLLI(shamt, rsd)) =
execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SLLI))
@@ -424,9 +423,9 @@ mapping clause assembly = C_SLLI(shamt, rsd)
union clause ast = C_LWSP : (bits(6), regidx)
mapping clause encdec_compressed = C_LWSP(ui76 @ ui5 @ ui42, rd)
- if rd != zreg & extensionEnabled(Ext_C)
+ if rd != zreg & extensionEnabled(Ext_Zca)
<-> 0b010 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10
- if rd != zreg & extensionEnabled(Ext_C)
+ if rd != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_LWSP(uimm, rd)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
@@ -442,9 +441,9 @@ mapping clause assembly = C_LWSP(uimm, rd)
union clause ast = C_LDSP : (bits(6), regidx)
mapping clause encdec_compressed = C_LDSP(ui86 @ ui5 @ ui43, rd)
- if rd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if rd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
- if rd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if rd != zreg & sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_LDSP(uimm, rd)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -460,9 +459,9 @@ mapping clause assembly = C_LDSP(uimm, rd)
union clause ast = C_SWSP : (bits(6), regidx)
mapping clause encdec_compressed = C_SWSP(ui76 @ ui52, rs2)
- if extensionEnabled(Ext_C)
+ if extensionEnabled(Ext_Zca)
<-> 0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10
- if extensionEnabled(Ext_C)
+ if extensionEnabled(Ext_Zca)
function clause execute (C_SWSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
@@ -476,9 +475,9 @@ mapping clause assembly = C_SWSP(uimm, rs2)
union clause ast = C_SDSP : (bits(6), regidx)
mapping clause encdec_compressed = C_SDSP(ui86 @ ui53, rs2)
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
<-> 0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10
- if sizeof(xlen) == 64 & extensionEnabled(Ext_C)
+ if sizeof(xlen) == 64 & extensionEnabled(Ext_Zca)
function clause execute (C_SDSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -494,9 +493,9 @@ mapping clause assembly = C_SDSP(uimm, rs2)
union clause ast = C_JR : (regidx)
mapping clause encdec_compressed = C_JR(rs1)
- if rs1 != zreg & extensionEnabled(Ext_C)
+ if rs1 != zreg & extensionEnabled(Ext_Zca)
<-> 0b100 @ 0b0 @ rs1 : regidx @ 0b00000 @ 0b10
- if rs1 != zreg & extensionEnabled(Ext_C)
+ if rs1 != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_JR(rs1)) =
execute(RISCV_JALR(zero_extend(0b0), rs1, zreg))
@@ -510,9 +509,9 @@ mapping clause assembly = C_JR(rs1)
union clause ast = C_JALR : (regidx)
mapping clause encdec_compressed = C_JALR(rs1)
- if rs1 != zreg & extensionEnabled(Ext_C)
+ if rs1 != zreg & extensionEnabled(Ext_Zca)
<-> 0b100 @ 0b1 @ rs1 : regidx @ 0b00000 @ 0b10
- if rs1 != zreg & extensionEnabled(Ext_C)
+ if rs1 != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_JALR(rs1)) =
execute(RISCV_JALR(zero_extend(0b0), rs1, ra))
@@ -526,9 +525,9 @@ mapping clause assembly = C_JALR(rs1)
union clause ast = C_MV : (regidx, regidx)
mapping clause encdec_compressed = C_MV(rd, rs2)
- if rd != zreg & rs2 != zreg & extensionEnabled(Ext_C)
+ if rd != zreg & rs2 != zreg & extensionEnabled(Ext_Zca)
<-> 0b100 @ 0b0 @ rd : regidx @ rs2 : regidx @ 0b10
- if rd != zreg & rs2 != zreg & extensionEnabled(Ext_C)
+ if rd != zreg & rs2 != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_MV(rd, rs2)) =
execute(RTYPE(rs2, zreg, rd, RISCV_ADD))
@@ -541,8 +540,8 @@ mapping clause assembly = C_MV(rd, rs2)
/* ****************************************************************** */
union clause ast = C_EBREAK : unit
-mapping clause encdec_compressed = C_EBREAK() if extensionEnabled(Ext_C)
- <-> 0b100 @ 0b1 @ 0b00000 @ 0b00000 @ 0b10 if extensionEnabled(Ext_C)
+mapping clause encdec_compressed = C_EBREAK() if extensionEnabled(Ext_Zca)
+ <-> 0b100 @ 0b1 @ 0b00000 @ 0b00000 @ 0b10 if extensionEnabled(Ext_Zca)
function clause execute C_EBREAK() =
execute(EBREAK())
@@ -553,9 +552,9 @@ mapping clause assembly = C_EBREAK() <-> "c.ebreak"
union clause ast = C_ADD : (regidx, regidx)
mapping clause encdec_compressed = C_ADD(rsd, rs2)
- if rsd != zreg & rs2 != zreg & extensionEnabled(Ext_C)
+ if rsd != zreg & rs2 != zreg & extensionEnabled(Ext_Zca)
<-> 0b100 @ 0b1 @ rsd : regidx @ rs2 : regidx @ 0b10
- if rsd != zreg & rs2 != zreg & extensionEnabled(Ext_C)
+ if rsd != zreg & rs2 != zreg & extensionEnabled(Ext_Zca)
function clause execute (C_ADD(rsd, rs2)) =
execute(RTYPE(rs2, rsd, rsd, RISCV_ADD))
diff --git a/model/riscv_insts_cdext.sail b/model/riscv_insts_zcd.sail
index 5571bef..fc608a4 100644
--- a/model/riscv_insts_cdext.sail
+++ b/model/riscv_insts_zcd.sail
@@ -6,20 +6,13 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/
-/* ********************************************************************* */
-/* This file specifies the compressed floating-point instructions.
- *
- * These instructions are only legal if misa[C] and misa[D]
- * are set.
- */
+enum clause extension = Ext_Zcd
+function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (sizeof(xlen) == 32 | sizeof(xlen) == 64)
-/* ****************************************************************** */
union clause ast = C_FLDSP : (bits(6), regidx)
-mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd) if extensionEnabled(Ext_Zcd)
+ <-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10 if extensionEnabled(Ext_Zcd)
function clause execute (C_FLDSP(uimm, rd)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -34,10 +27,8 @@ mapping clause assembly = C_FLDSP(uimm, rd)
/* ****************************************************************** */
union clause ast = C_FSDSP : (bits(6), regidx)
-mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2) if extensionEnabled(Ext_Zcd)
+ <-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10 if extensionEnabled(Ext_Zcd)
function clause execute (C_FSDSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -52,10 +43,8 @@ mapping clause assembly = C_FSDSP(uimm, rs2)
/* ****************************************************************** */
union clause ast = C_FLD : (bits(5), cregidx, cregidx)
-mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd) if extensionEnabled(Ext_Zcd)
+ <-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_Zcd)
function clause execute (C_FLD(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -72,10 +61,8 @@ mapping clause assembly = C_FLD(uimm, rsc, rdc)
/* ****************************************************************** */
union clause ast = C_FSD : (bits(5), cregidx, cregidx)
-mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2) if extensionEnabled(Ext_Zcd)
+ <-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00 if extensionEnabled(Ext_Zcd)
function clause execute (C_FSD(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b000);
diff --git a/model/riscv_insts_cfext.sail b/model/riscv_insts_zcf.sail
index 976425d..ce601de 100644
--- a/model/riscv_insts_cfext.sail
+++ b/model/riscv_insts_zcf.sail
@@ -14,12 +14,14 @@
*/
/* ****************************************************************** */
+
+enum clause extension = Ext_Zcf
+function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & sizeof(xlen) == 32
+
union clause ast = C_FLWSP : (bits(6), regidx)
-mapping clause encdec_compressed = C_FLWSP(ui76 @ ui5 @ ui42, rd)
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
- <-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
+mapping clause encdec_compressed = C_FLWSP(ui76 @ ui5 @ ui42, rd) if extensionEnabled(Ext_Zcf)
+ <-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10 if extensionEnabled(Ext_Zcf)
function clause execute (C_FLWSP(imm, rd)) = {
let imm : bits(12) = zero_extend(imm @ 0b00);
@@ -34,10 +36,8 @@ mapping clause assembly = C_FLWSP(imm, rd)
/* ****************************************************************** */
union clause ast = C_FSWSP : (bits(6), regidx)
-mapping clause encdec_compressed = C_FSWSP(ui76 @ ui52, rs2)
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
- <-> 0b111 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
+mapping clause encdec_compressed = C_FSWSP(ui76 @ ui52, rs2) if extensionEnabled(Ext_Zcf)
+ <-> 0b111 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10 if extensionEnabled(Ext_Zcf)
function clause execute (C_FSWSP(uimm, rs2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
@@ -52,10 +52,8 @@ mapping clause assembly = C_FSWSP(uimm, rs2)
/* ****************************************************************** */
union clause ast = C_FLW : (bits(5), cregidx, cregidx)
-mapping clause encdec_compressed = C_FLW(ui6 @ ui53 @ ui2, rs1, rd)
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
- <-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
+mapping clause encdec_compressed = C_FLW(ui6 @ ui53 @ ui2, rs1, rd) if extensionEnabled(Ext_Zcf)
+ <-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_Zcf)
function clause execute (C_FLW(uimm, rsc, rdc)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
@@ -72,10 +70,8 @@ mapping clause assembly = C_FLW(uimm, rsc, rdc)
/* ****************************************************************** */
union clause ast = C_FSW : (bits(5), cregidx, cregidx)
-mapping clause encdec_compressed = C_FSW(ui6 @ ui53 @ ui2, rs1, rs2)
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
- <-> 0b111 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00
- if sizeof(xlen) == 32 & extensionEnabled(Ext_C) & extensionEnabled(Ext_F)
+mapping clause encdec_compressed = C_FSW(ui6 @ ui53 @ ui2, rs1, rs2) if extensionEnabled(Ext_Zcf)
+ <-> 0b111 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00 if extensionEnabled(Ext_Zcf)
function clause execute (C_FSW(uimm, rsc1, rsc2)) = {
let imm : bits(12) = zero_extend(uimm @ 0b00);
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail
index 0f4abd0..ea41ce4 100644
--- a/model/riscv_jalr_seq.sail
+++ b/model/riscv_jalr_seq.sail
@@ -24,7 +24,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
},
Ext_ControlAddr_OK(addr) => {
let target = [addr with 0 = bitzero]; /* clear addr[0] */
- if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C)) then {
+ if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca)) then {
handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
} else {
diff --git a/model/riscv_step.sail b/model/riscv_step.sail
index 6f2a158..cd858c3 100644
--- a/model/riscv_step.sail
+++ b/model/riscv_step.sail
@@ -54,7 +54,7 @@ function step(step_no : int) -> bool = {
print_instr("[" ^ dec_str(step_no) ^ "] [" ^ to_str(cur_privilege) ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ to_str(ast));
};
/* check for RVC once here instead of every RVC execute clause. */
- if extensionEnabled(Ext_C) then {
+ if extensionEnabled(Ext_Zca) then {
nextPC = PC + 2;
(execute(ast), true)
} else {
generated by cgit v1.1 at 2024-10-04 03:21:27 +0000